Directorio
ANTONIO JOSE ACOSTA JIMENEZ
Categoría
Catedrático de Universidad
Departamento
Área
Electrónica
Docencia
Asignaturas que imparte
- Circuitos Eléctricos: Teoría e Instrumentación
- Métodos Numéricos y de Simulación
- Circuitos Eléctricos: Teoría e Instrumentación
- Nanomateriales y Nanotecnología
- Circuitos Eléctricos: Teoría e Instrumentación
- Métodos Numéricos y de Simulación
- Nanomateriales y Nanotecnología
- Nanomateriales y Nanotecnología
- Métodos Numéricos y de Simulación
- Circuitos Eléctricos. Teoría e Instrumentación
- Transceptores Inalámbricos: Estándares, Técnicas y Arquitecturas
- Técnicas Avanzadas de Diseño
Investigación
Grupo de investigación
DISEÑO DE CIRCUITOS INTEGRADOS DIGITALES Y MIXTOS (DISEÑO DE CIRCUITOS INTEGRADOS)
Proyectos y contratos de investigación
DISEÑO PARA OPTIMIZACION COMBINADA DE RUIDO Y CONSUMO DE POTENCIA DE CIRCUITOS INTEGRADOS CMOS VLSI DIGITALES Y DE SEÑAL MIXTA (TEC2004-01509 - Responsable)
DISEÑO DE SISTEMAS DIGITALES MICRO-NANOELECTRÓNICOS DE ALTAS PRESTACIONES (EXC/2005/TIC-635 - Investigador/a)
TÉCNICAS INTEGRALES DE CONTROL DE CORRIENTE DE POLARIZACIÓN EN CIRCUITOS INTEGRADOS NANOMÉTRICOS DIGITALES Y DE SEÑAL MIXTA (TEC2007-65105/MIC - Responsable)
ACCION COMPLEMENTARIA "PROYECTOS PARA FP7 (TEC2007-30739-E - Investigador/a)
DISEÑO MICROELECTRÓNICO PARA AUTENTICACIÓN CRIPTO-BIOMÉTRICA (P08-TIC-3674 - Investigador/a)
AYUDA A LA CONSOLIDACION DE GRUPOS DE INVESTIGACION - TIC 180 CONVOCATORIA 2007 (P-2008/282 - Investigador/a)
DESARROLLO DE UNA RED DISTRIBUIDA DE SENSORES ACÚSTICOS PARA SEGUIMIENTO DE ESPECIES EN PELIGRO DE EXTINCIÓN (200450E647 - Investigador/a)
AYUDA A LA CONSOLIDACIÓN DE GRUPOS DE INVESTIGACIÓN - TIC 180 CONVOCATORIA 2009 (2009/00001259 - Investigador/a)
MOBY-DIC MODEL-BASED SYNTHESIS OF DIGITAL ELECTRONIC CIRCUITS FOR EMBEDDED CONTROL (FP7-ICT-2009-4 - Responsable)
AYUDA A LA CONSOLIDACIÓN DE GRUPOS DE INVESTIGACIÓN - TIC 180 CONVOCATORIA 2008 (P2009/438 - Investigador/a)
FORTALECIMIENTO INSTITUC. DE LAS ACTI. DE POSTGRADO E INVEST. EN SISTEMAS ELECTRÓNICOS INTEGRADOS EN EL INSTITUTO SUPERIOR POLITÉCNICO JOSE A. ECHEVAR (D/024124/09 - Investigador/a)
CIRCUITOS INTEGRADOS PARA TRANSMISIÓN DE INFORMACIÓN ESPECIALMENTE SEGURA (TEC2010-16870 - Investigador/a)
FORTIN: Fortalecimiento institucional de las actividades de postgrado e investigación en sistemas electrónicos integrados en el Instituto Superior Pol (D030769/10 - Investigador/a)
VERIFICACION Y DISEÑO DE CIRCUITOS INTEGRADOS DIGITALES CMOS VLSI DE BAJO RUIDO DE CONMUTACION PARA APLICACIONES DE SEÑAL MIXTA (TIC2001-2283 - Investigador/a)
MODEL: MODELADO DE LA OPERACION DINAMICA DE COMPONENTES LOGICOS CMOS EN TECNOLOGIAS SUBMICROMICAS PARA ANALISIS DE ALTAS PRESTACIONES (TIC2000-1350 - Investigador/a)
TEMPORIZACION EN CIRCUITOS INTEGRADOS DIGITALES CMOS (TXT98-1693 - Investigador/a)
SINTESIS DE CIRCUITOS DIFUSOS ANALOGICOS DIGITALES PARA APLICACIONES ESPECIFICAS.TIC98-0869 (TIC98-0869 - Investigador/a)
TEMPORIZACION EN CIRCUITOS INTEGRADOS DIGITALES CMOS (TXT96-2284 - Investigador/a)
SINCRONIZADOR EN FRECUENCIA PARA SISTEMAS OFDM DE BANDA ANCHA EN APLICACIONES NETWORKING SOBRE REDES RESIDENCIALES EN ENERGÍA ELÉCTRICA (SINCROFDM) (SAINCO1-2003 - Responsable)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-035/03 - Investigador/a)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (ESPRIT 33485-MICROCARD) (OG-064/00 - Investigador/a)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (ESPRIT 26354-ASTERIS) (OG-067/00 - Investigador/a)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (68/83) (OG-084/04 - Investigador/a)
SCARoT: Side-Channel Attacks on Root of Trust (US-1380823 - Investigador Principal Consolidado)
Transferencia a la Universidad Tecnológica de La Habana de tecnologías avanzadas de diseño de sistemas empotrados sobre hardware reconfigurable (Resolución US - Investigador/a)
Diseño VLSI de módulo digital serializador (framing) de altas prestaciones para un sensor quad-linear de alta velocidad de 16k píxeles. (2154/0713 - Investigador/a)
Integración y Validación en Laboratorio de Contramedidas Frente a Ataques Laterales en Criptocircuitos Microelectrónicos (TEC2016-80549-R - Responsable)
Cesar: Circuitos Microelectrónicos Seguros Frente a Ataques Laterales (TEC2013-45523-R - Responsable)
CESAR: CIRCUITOS MICROELECTRONICOS SEGUROS FRENTE A ATAQUES LATERALES (TEC2013-45523-R - Responsable)
Diseminación de conocimiento y prospectiva de transferencia tecnológica TIC en el área de la seguridad y la cripto-biometría (Participante)
Libros publicados
Acosta-Jimenez, Antonio Jose:
La Nanotecnología, explorando un cosmos en miniatura. RBA-Editores. 2016. 978-84-473-8382-5
La Nanotecnología, explorando un cosmos en miniatura. RBA-Editores. 2016. 978-84-473-8382-5
Hochet-,B.;Acosta-Jimenez, Antonio Jose;Bellido-Diaz, Manuel Jesus:
INTEGRATED CIRCUIT DESIGN. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION. SPRINGER-VERLAG. 2002. 3-540-44143-3
INTEGRATED CIRCUIT DESIGN. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION. SPRINGER-VERLAG. 2002. 3-540-44143-3
Acosta-Jimenez, Antonio Jose;Barriga-Barros, Angel;Bellido-Diaz, Manuel Jesus;Juan-Chico, Jorge;Valencia-Barrero, Manuel:
TEMPORIZACIÓN EN CIRCUITOS INTEGRADOS DIGITALES CMOS. MARCOMBO. BOIXAREU EDITORES. 2000. 84-267-1246-0
TEMPORIZACIÓN EN CIRCUITOS INTEGRADOS DIGITALES CMOS. MARCOMBO. BOIXAREU EDITORES. 2000. 84-267-1246-0
Capítulos en Libros
Tena-Sánchez, Erica;Potestad, Francisco Eugenio;Parra-Fernández, María Del Pilar;Baena-Oliva, Maria Carmen;Valencia-Barrero, Manuel;Jimenez-Fernandez, Carlos Jesus;Acosta-Jimenez, Antonio Jose:
DESIGN AND SECURITY EVALUATION OF SECURE CRYPTOHARDWARE (FPGA AND ASIC) AGAINST HACKERS EXPLOITING SIDE-CHANNEL INFORMATION DESIGN AND SECURITY EVALUA. Pág. 47-50. 3ciencias (www.3ciencias.com). 3ciencias (www.3ciencias.com). 2022.
DESIGN AND SECURITY EVALUATION OF SECURE CRYPTOHARDWARE (FPGA AND ASIC) AGAINST HACKERS EXPLOITING SIDE-CHANNEL INFORMATION DESIGN AND SECURITY EVALUA. Pág. 47-50. 3ciencias (www.3ciencias.com). 3ciencias (www.3ciencias.com). 2022.
Bellido-Diaz, Manuel Jesus;Barriga-Barros, Angel;Acosta-Jimenez, Antonio Jose:
ASYNCRONOUS SEQUENTIAL LOGIC. Pág. 742-749. DESCONOCIDO. DESCONOCIDO. 1999.
ASYNCRONOUS SEQUENTIAL LOGIC. Pág. 742-749. DESCONOCIDO. DESCONOCIDO. 1999.
Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel;Huertas-Diaz, Jose Luis:
ANALYSIS OF METASTABLE OPERATION IN A CMOS DYNAMIC D-LATCH. Pág. 143-157. KLUWER ACADEMIC PUBLISHERS. KLUWER ACADEMIC PUBLISHERS. 1997.
ANALYSIS OF METASTABLE OPERATION IN A CMOS DYNAMIC D-LATCH. Pág. 143-157. KLUWER ACADEMIC PUBLISHERS. KLUWER ACADEMIC PUBLISHERS. 1997.
Asistencia a congresos
Potestad, Francisco Eugenio;Tena-Sánchez, Erica;Chaves, Ricardo;Valencia-Barrero, Manuel;Acosta-Jimenez, Antonio Jose;Jimenez-Fernandez, Carlos Jesus:
Hamming-code based fault detection desing methodology for block ciphers. Ponencia en Congreso. IEEE International Symposium on Circuits and Systems (ISCAS). , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Facultad de Ciencias Económicas y Empresariales. Universidad de Sevilla. 2020
Hamming-code based fault detection desing methodology for block ciphers. Ponencia en Congreso. IEEE International Symposium on Circuits and Systems (ISCAS). , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Facultad de Ciencias Económicas y Empresariales. Universidad de Sevilla. 2020
Tena-Sánchez, Erica;Delgado-lozano, Ignacio M.;Nuñez-Martínez, Juan;Acosta-Jimenez, Antonio Jose:
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. Comunicación en congreso. XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS . - Lyon, Francia, Francia. 2018
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. Comunicación en congreso. XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS . - Lyon, Francia, Francia. 2018
Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose:
Effect of temperature variation in experimental DPA and DEMA attacks. Poster en Congreso. International Workshop on Power and Timing Modeling, Optimization and Simulation. Costa Brava (Spain). 2018
Effect of temperature variation in experimental DPA and DEMA attacks. Poster en Congreso. International Workshop on Power and Timing Modeling, Optimization and Simulation. Costa Brava (Spain). 2018
Canas-moreno, Salvador;Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose:
A low-cost FPGA-based platform to perform fast Power/Electromagnetic Attacks on cryptographic circuits. Conferencia Congreso no publicada. XXXI Design of Circuits and Integrated Systems Conference. Granada. 2016
A low-cost FPGA-based platform to perform fast Power/Electromagnetic Attacks on cryptographic circuits. Conferencia Congreso no publicada. XXXI Design of Circuits and Integrated Systems Conference. Granada. 2016
Tena-Sánchez, Erica;Durán-menor De Gaspar, Irene;Canas-moreno, Salvador;Acosta-Jimenez, Antonio Jose:
Vulnerability Evaluation and Secure Design Methodology of Cryptohardware for ASIC-embedded Secure Applications to Prevent Side-Channel Attacks. Conferencia Congreso no publicada. Workshop on Trustworthy Manufacturing and Utilization of Secure Devices TRUDEVICE 2016. . Barcelona. 2016
Vulnerability Evaluation and Secure Design Methodology of Cryptohardware for ASIC-embedded Secure Applications to Prevent Side-Channel Attacks. Conferencia Congreso no publicada. Workshop on Trustworthy Manufacturing and Utilization of Secure Devices TRUDEVICE 2016. . Barcelona. 2016
Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose;Nuñez-Martínez, Juan:
Secure Cryptographic Hardware Implementation Issues for High-Performance Applications. Poster en Congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). BREMEN, ALEMANIA. 2016
Secure Cryptographic Hardware Implementation Issues for High-Performance Applications. Poster en Congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). BREMEN, ALEMANIA. 2016
Acosta-Jimenez, Antonio Jose;Barriga-Barros, Angel;Perez-Verdu, Maria Belen;Huertas-Diaz, Jose Luis:
Experiencia de puesta en marcha y desarrollo de un Máster on-line en Microelectrónica. Comunicación en congreso. XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica. Sevilla (España). 2016
Experiencia de puesta en marcha y desarrollo de un Máster on-line en Microelectrónica. Comunicación en congreso. XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica. Sevilla (España). 2016
Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose:
Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. ESTORIL (PORTUGAL). 2015
Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. ESTORIL (PORTUGAL). 2015
Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose:
Design and Characterization of Cryptohardware for ASIC-embedded Secure Applications to Prevent Power Analysis Attacks. Conferencia Congreso no publicada. 17th International Workshop on Cryptographic Hardware and Embedded Systems. Saint Malo, Francia. 2015
Design and Characterization of Cryptohardware for ASIC-embedded Secure Applications to Prevent Power Analysis Attacks. Conferencia Congreso no publicada. 17th International Workshop on Cryptographic Hardware and Embedded Systems. Saint Malo, Francia. 2015
Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose:
DPA Vulnerability Analysis on Trivium Stream Cipher using an Optimized Power Model. Comunicación en congreso. 2015 IEEE International Symposium on Circuits and Systems (ISCAS),. Lisboa-Portugal. 2015
DPA Vulnerability Analysis on Trivium Stream Cipher using an Optimized Power Model. Comunicación en congreso. 2015 IEEE International Symposium on Circuits and Systems (ISCAS),. Lisboa-Portugal. 2015
Martínez-Rodríguez, Macarena Cristina;Brox-Jimenez, Piedad;Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose;Baturone-Castillo, Iluminada:
Programmable ASICs for model predictive control. Comunicación en congreso. IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGIES 2015. Sevilla (Spain). 2015
Programmable ASICs for model predictive control. Comunicación en congreso. IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGIES 2015. Sevilla (Spain). 2015
Tena-Sánchez, Erica;Castro-Ramirez, Javier;Acosta-Jimenez, Antonio Jose:
Design and Test of a Low-Power 90nm Xor/Xnor Gate for Cryptographic Applications. Comunicación en congreso. International Workshop On Power And Timing Modeling, Optimization And Simulations. Palma de Mallorca. 2014
Design and Test of a Low-Power 90nm Xor/Xnor Gate for Cryptographic Applications. Comunicación en congreso. International Workshop On Power And Timing Modeling, Optimization And Simulations. Palma de Mallorca. 2014
Tena-Sánchez, Erica;Castro-Ramirez, Javier;Acosta-Jimenez, Antonio Jose:
Low-Power Differential Logic Gates for DPA Resistant Circuits. Poster en Congreso. Euromicro Conference on Digital System Design. Verona. 2014
Low-Power Differential Logic Gates for DPA Resistant Circuits. Poster en Congreso. Euromicro Conference on Digital System Design. Verona. 2014
Acosta-Jimenez, Antonio Jose:
Low Power and Security Trade-off in Hardware: From True Random Number Generators to DPA Resilience. Sesión plenaria en Congreso. Energy Secure Systems Architecture Workshop . MINNEAPOLIS, EE. UU.. 2014
Low Power and Security Trade-off in Hardware: From True Random Number Generators to DPA Resilience. Sesión plenaria en Congreso. Energy Secure Systems Architecture Workshop . MINNEAPOLIS, EE. UU.. 2014
Tena-Sánchez, Erica;Castro-Ramirez, Javier;Acosta-Jimenez, Antonio Jose:
Automatic and Systematic Test Toolset for Digital ASICs. Comunicación en congreso. DCIS 2013. Donostia - San Sebastián (España). 2013
Automatic and Systematic Test Toolset for Digital ASICs. Comunicación en congreso. DCIS 2013. Donostia - San Sebastián (España). 2013
Tena-Sánchez, Erica;Castro-Ramirez, Javier;Acosta-Jimenez, Antonio Jose:
Automatic and Systematic Control of Experimental Data Measurements on ASICs. Comunicación en congreso. 19th Symposium IMEKO TC 4 Symposium. Barcelona, - BARCELONA, ESPAÑA. 2013
Automatic and Systematic Control of Experimental Data Measurements on ASICs. Comunicación en congreso. 19th Symposium IMEKO TC 4 Symposium. Barcelona, - BARCELONA, ESPAÑA. 2013
Martínez-Rodríguez, Macarena Cristina;Brox-Jimenez, Piedad;Castro-Ramirez, Javier;Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose;Baturone-Castillo, Iluminada:
ASIC-in-the-loop methodology for verification of piecewise affine controllers. Comunicación en congreso. 19th International Conference on Electronics, Circuits and Systems. SEVILLE (SPAIN). 2012
ASIC-in-the-loop methodology for verification of piecewise affine controllers. Comunicación en congreso. 19th International Conference on Electronics, Circuits and Systems. SEVILLE (SPAIN). 2012
EIROA-LORENZO, SUSANA;Baturone-Castillo, Iluminada;Acosta-Jimenez, Antonio Jose;DÁVILA-MURO, JORGE:
Using Physical Unclonable Functions for Hardware Authentication: A Survey. Ponencia en Congreso. Desing of Circuits and Integrated Systems (DCIS). LANZAROTE. 2010
Using Physical Unclonable Functions for Hardware Authentication: A Survey. Ponencia en Congreso. Desing of Circuits and Integrated Systems (DCIS). LANZAROTE. 2010
Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose:
MASTER-SLAVE FLIP-FLOP OPTIMIZATION FOR FINE-GRAINED CLOCK-GATING APPLICATIONS. Comunicación en congreso. IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS () (.2010.BRASIL). BRASIL. 2010
MASTER-SLAVE FLIP-FLOP OPTIMIZATION FOR FINE-GRAINED CLOCK-GATING APPLICATIONS. Comunicación en congreso. IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS () (.2010.BRASIL). BRASIL. 2010
Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose:
REVISITING CLOCK-GATING: THE COMMON PLACE FOR POWER REDUCTION. Comunicación en congreso. XVI WORKSHOP IBERCHIP () (.2010.IGUAZU FALLS, BRASIL). IGUAZU FALLS, BRASIL. 2010
REVISITING CLOCK-GATING: THE COMMON PLACE FOR POWER REDUCTION. Comunicación en congreso. XVI WORKSHOP IBERCHIP () (.2010.IGUAZU FALLS, BRASIL). IGUAZU FALLS, BRASIL. 2010
Castro-Ramirez, Javier;Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose:
AN IMPROVED DIFFERENTIAL PULL-DOWN NETWORK LOGIC CONFIGURATION FOR DPA RESISTANT CIRCUITS. Comunicación en congreso. THE 22ND INTERNATIONAL CONFERENCE ON MICROELECTRONICS. EL CAIRO, EGIPTO. 2010
AN IMPROVED DIFFERENTIAL PULL-DOWN NETWORK LOGIC CONFIGURATION FOR DPA RESISTANT CIRCUITS. Comunicación en congreso. THE 22ND INTERNATIONAL CONFERENCE ON MICROELECTRONICS. EL CAIRO, EGIPTO. 2010
Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose:
OPTIMIZATION OF CLOCK-GATING STRUCTURES FOR LOW-LEAKAGE HIGH-PERFORMANCE APPLICATIONS. Comunicación en congreso. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1979-1982, Jun. 2010. PARIS, FRANCE. 2010
OPTIMIZATION OF CLOCK-GATING STRUCTURES FOR LOW-LEAKAGE HIGH-PERFORMANCE APPLICATIONS. Comunicación en congreso. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1979-1982, Jun. 2010. PARIS, FRANCE. 2010
Camuñas-Mesa, Luis Alejandro;Linares-Barranco, Alejandro;Acosta-Jimenez, Antonio Jose;Serrano-Gotarredona, Maria Teresa;Linares-Barranco, Bernabe:
IMPROVED AER CONVOLUTION CHIP FOR VISION PROCESSING WITH HIGHER RESOLUTION AND NEW FUNCTIONALITIES. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (24) (24.2009.Zaragoza). Zaragoza. 2009
IMPROVED AER CONVOLUTION CHIP FOR VISION PROCESSING WITH HIGHER RESOLUTION AND NEW FUNCTIONALITIES. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (24) (24.2009.Zaragoza). Zaragoza. 2009
Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose:
SWITCHING NOISE OPTIMIZATION IN THE WAKE-UP PHASE OF LEAKAGE-AWARE POWER GATING STRUCTURES. Comunicación en congreso. NINETEENTH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION () (.2009.DELFT, PAÍSES BAJOS). DELFT, PAÍSES BAJOS. 2009
SWITCHING NOISE OPTIMIZATION IN THE WAKE-UP PHASE OF LEAKAGE-AWARE POWER GATING STRUCTURES. Comunicación en congreso. NINETEENTH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION () (.2009.DELFT, PAÍSES BAJOS). DELFT, PAÍSES BAJOS. 2009
Villegas-Calvo, Jose Alberto;Fiorelli-Martegani, Rafaella Bianca;Gines-Arteaga, Antonio Jose;Doldan-Lorenzo, Ricardo;Jalon-Victori, Mª Angeles;Acosta-Jimenez, Antonio Jose;Peralias-Macias, Eduardo;Vazquez-Garcia De La Vega, Diego;Rueda-Rueda, Adoracion:
A 2.5MHZ BANDPASS ACTIVE COMPLEX FILTER WITH 2.4MHZ BANDWIDTH FOR WIRELESS COMMUNICATIONS. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (23) (23.2008.GRENOBLE (FRANCIA)). GRENOBLE (FRANCIA). 2008
A 2.5MHZ BANDPASS ACTIVE COMPLEX FILTER WITH 2.4MHZ BANDWIDTH FOR WIRELESS COMMUNICATIONS. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (23) (23.2008.GRENOBLE (FRANCIA)). GRENOBLE (FRANCIA). 2008
Acosta-Jimenez, Antonio Jose;Rio-Fernandez, Rocio Del;Rodriguez-Vazquez, Angel:
LA SIMULACIÓN ELÉCTRICA EN EL TRABAJO ACADÉMICAMENTE DIRIGIDO COMO VEHÍCULO DOCENTE PARA LA ENSEÑANZA DE LA ELECTRÓNICA. Comunicación en congreso. VIII CONGRESO DE TECNOLOGÍAS APLICADAS A LA ENSEÑANZA DE LA ELECTRONICA (TAEE) 2008 () (.2008.MADRID). . 2008
LA SIMULACIÓN ELÉCTRICA EN EL TRABAJO ACADÉMICAMENTE DIRIGIDO COMO VEHÍCULO DOCENTE PARA LA ENSEÑANZA DE LA ELECTRÓNICA. Comunicación en congreso. VIII CONGRESO DE TECNOLOGÍAS APLICADAS A LA ENSEÑANZA DE LA ELECTRONICA (TAEE) 2008 () (.2008.MADRID). . 2008
Camuñas-Mesa, Luis Alejandro;Acosta-Jimenez, Antonio Jose;Serrano-Gotarredona, Maria Teresa;Linares-Barranco, Bernabe:
FULLY DIGITAL AER CONVOLUTION CHIP FOR VISION PROCESSING. Comunicación en congreso. ISCAS 2008 () (.2008.SEATTLE, WASHINGTON, USA). SEATTLE, WASHINGTON, USA. 2008
FULLY DIGITAL AER CONVOLUTION CHIP FOR VISION PROCESSING. Comunicación en congreso. ISCAS 2008 () (.2008.SEATTLE, WASHINGTON, USA). SEATTLE, WASHINGTON, USA. 2008
Castro-Ramirez, Javier;Acosta-Jimenez, Antonio Jose;Vesterbacka, Mark:
GEOMETRY OPTIMIZATION IN BASIC CMOS CELLS FOR IMPROVED POWER, LEAKAGE, AND NOISE PERFORMANCES. Comunicación en congreso. INT. CONF. ON ADVANCES IN ELECTRONICS AND MICRO-ELECTRONICS (ENICS'08) () (.2008.VALENCIA). . 2008
GEOMETRY OPTIMIZATION IN BASIC CMOS CELLS FOR IMPROVED POWER, LEAKAGE, AND NOISE PERFORMANCES. Comunicación en congreso. INT. CONF. ON ADVANCES IN ELECTRONICS AND MICRO-ELECTRONICS (ENICS'08) () (.2008.VALENCIA). . 2008
Gines-Arteaga, Antonio Jose;Doldan-Lorenzo, Ricardo;Villegas-Calvo, Jose Alberto;Acosta-Jimenez, Antonio Jose;Jalon-Victori, Mª Angeles;Vazquez-Garcia De La Vega, Diego;Rueda-Rueda, Adoracion;Peralias-Macias, Eduardo:
A 1.2V 5.14MW QUADRATURE FREQUENCY SYNTHESIZER IN 90NM CMOS TECHNOLOGY FOR 2.4GHZ ZIGBEE APPLICATIONS. Comunicación en congreso. IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS () (.2008.MACAU (CHINA)). MACAU (CHINA). 2008
A 1.2V 5.14MW QUADRATURE FREQUENCY SYNTHESIZER IN 90NM CMOS TECHNOLOGY FOR 2.4GHZ ZIGBEE APPLICATIONS. Comunicación en congreso. IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS () (.2008.MACAU (CHINA)). MACAU (CHINA). 2008
Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar;Valencia-Barrero, Manuel;Acosta-Jimenez, Antonio Jose:
ASYMMETRIC CLOCK DRIVER FOR IMPROVED POWER AND NOISE PERFORMANCES. Comunicación en congreso. IEEE International Symposium on Circuits and Systems (ISCAS 2007). New Orleans, USA. 2007
ASYMMETRIC CLOCK DRIVER FOR IMPROVED POWER AND NOISE PERFORMANCES. Comunicación en congreso. IEEE International Symposium on Circuits and Systems (ISCAS 2007). New Orleans, USA. 2007
Acosta-Jimenez, Antonio Jose;Mora-Gutierrez, Jose Miguel;Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar:
EFFECTS OF BUFFER INSERTION ON THE AVERAGE/PEAK POWER RATIO IN CMOS VLSI DIGITAL CIRCUITS. Comunicación en congreso. VLSI CIRCUITS AND SYSTEMS CONFERENCE SPIE 2007 () (.2007.MASPALOMAS, ESPAÑA). MASPALOMAS, ESPAÑA. 2007
EFFECTS OF BUFFER INSERTION ON THE AVERAGE/PEAK POWER RATIO IN CMOS VLSI DIGITAL CIRCUITS. Comunicación en congreso. VLSI CIRCUITS AND SYSTEMS CONFERENCE SPIE 2007 () (.2007.MASPALOMAS, ESPAÑA). MASPALOMAS, ESPAÑA. 2007
Camuñas-Mesa, Luis Alejandro;Acosta-Jimenez, Antonio Jose;Serrano-Gotarredona, Maria Teresa;Linares-Barranco, Bernabe;Serrano-Gotarredona, Rafael:
IMAGE PROCESSING ARCHITECTURE BASED ON A FULLY DIGITAL AER CONVOLUTION CHIP. Comunicación en congreso. XXII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS2007) (22) (22.2007.SEVILLA(ESPAÑA)). SEVILLA(ESPAÑA). 2007
IMAGE PROCESSING ARCHITECTURE BASED ON A FULLY DIGITAL AER CONVOLUTION CHIP. Comunicación en congreso. XXII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS2007) (22) (22.2007.SEVILLA(ESPAÑA)). SEVILLA(ESPAÑA). 2007
Rimolo-Donadio,Renato;Acosta-Jimenez, Antonio Jose;Krautschneider-,Wolfgang:
ASYNCHRONOUS STAGGERED SET/RESET TECHNIQUES FOR LOW-NOISE APPLICATIONS. Comunicación en congreso. ISCAS 2007 () (.2007.NUEVA ORLEANS, EE.UU.). NUEVA ORLEANS, EE.UU.. 2007
ASYNCHRONOUS STAGGERED SET/RESET TECHNIQUES FOR LOW-NOISE APPLICATIONS. Comunicación en congreso. ISCAS 2007 () (.2007.NUEVA ORLEANS, EE.UU.). NUEVA ORLEANS, EE.UU.. 2007
Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar;Valencia-Barrero, Manuel;Acosta-Jimenez, Antonio Jose:
A SWITCHING NOISE VISION OF THE OPTIMIZATION TECHNIQUES FOR LOW-POWER SYNTHESIS. Comunicación en congreso. EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN ECCTD () (.2007.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2007
A SWITCHING NOISE VISION OF THE OPTIMIZATION TECHNIQUES FOR LOW-POWER SYNTHESIS. Comunicación en congreso. EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN ECCTD () (.2007.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2007
Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose:
A METHODOLOGY FOR SWITCHING NOISE ESTIMATION AT A GATE LEVEL. Comunicación en congreso. VLSI CIRCUITS AND SYSTEMS CONFERENCE SPIE 2007 () (.2007.MASPALOMAS, ESPAÑA). MASPALOMAS, ESPAÑA. 2007
A METHODOLOGY FOR SWITCHING NOISE ESTIMATION AT A GATE LEVEL. Comunicación en congreso. VLSI CIRCUITS AND SYSTEMS CONFERENCE SPIE 2007 () (.2007.MASPALOMAS, ESPAÑA). MASPALOMAS, ESPAÑA. 2007
Serrano-Gotarredona, Rafael;Serrano-Gotarredona, Maria Teresa;Acosta-Jimenez, Antonio Jose;Linares-Barranco, Alejandro;Jimenez-Moreno, Gabriel;Civit-Balcells, Antonio Abad;Linares-Barranco, Bernabe:
SPIKE EVENTS PROCESSING FOR VISION SYSTEMS. Ponencia en Congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEM (40) (40.2007.NEW ORLEANS, LUSIANA, USA). NEW ORLEANS, LUSIANA, USA. 2007
SPIKE EVENTS PROCESSING FOR VISION SYSTEMS. Ponencia en Congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEM (40) (40.2007.NEW ORLEANS, LUSIANA, USA). NEW ORLEANS, LUSIANA, USA. 2007
Jiménez-Naharro, Raúl;Parra-Fernández, María Del Pilar;Sanmartin-Rodriguez, Pedro Mario;Acosta-Jimenez, Antonio Jose:
Optimization of master-slave Flip-Flops for high performance applications.. Comunicación en congreso. International workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2006). Montpellier (France). 2006
Optimization of master-slave Flip-Flops for high performance applications.. Comunicación en congreso. International workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2006). Montpellier (France). 2006
Serrano-Gotarredona, Rafael;Serrano-Gotarredona, Maria Teresa;Linares-Barranco, Bernabe;Acosta-Jimenez, Antonio Jose;Camuñas-Mesa, Luis Alejandro:
A BIOINSPIRED EVENT-BASED REAL-TIME IMAGE PROCESSOR. Comunicación en congreso. CONFERENCE ON BIOMEDICAL, ROBOTICS AND BIOMECHATRONICS () (.2006.PISA, ITALY). PISA, ITALY. 2006
A BIOINSPIRED EVENT-BASED REAL-TIME IMAGE PROCESSOR. Comunicación en congreso. CONFERENCE ON BIOMEDICAL, ROBOTICS AND BIOMECHATRONICS () (.2006.PISA, ITALY). PISA, ITALY. 2006
Serrano-Gotarredona, Rafael;Serrano-Gotarredona, Maria Teresa;Acosta-Jimenez, Antonio Jose;Linares-Barranco, Bernabe:
AN ARBITRARY KERNEL CONVOLUTION AER-TRANSCEIVER CHIP FOR REAL-TIME MAGE FILTERING. Comunicación en congreso. ISCAS 2006 () (.2006.KOS, GRECIA). KOS, GRECIA. 2006
AN ARBITRARY KERNEL CONVOLUTION AER-TRANSCEIVER CHIP FOR REAL-TIME MAGE FILTERING. Comunicación en congreso. ISCAS 2006 () (.2006.KOS, GRECIA). KOS, GRECIA. 2006
Serrano-Gotarredona, Rafael;Linares-Barranco, Bernabe;Serrano-Gotarredona, Maria Teresa;Acosta-Jimenez, Antonio Jose;Linares-Barranco, Alejandro;Paz-Vicente, Rafael;Gómez-Rodríguez, Francisco De Asís;Jimenez-Moreno, Gabriel;Civit-Balcells, Antonio Abad:
HIGH-SPEED IMAGE PROCESSING WITH AER-BASED COMPONENTS. Comunicación en congreso. ISCAS 2006 () (.2006.KOS, GRECIA). KOS, GRECIA. 2006
HIGH-SPEED IMAGE PROCESSING WITH AER-BASED COMPONENTS. Comunicación en congreso. ISCAS 2006 () (.2006.KOS, GRECIA). KOS, GRECIA. 2006
Serrano-Gotarredona, Rafael;Serrano-Gotarredona, Maria Teresa;Acosta-Jimenez, Antonio Jose;Linares-Barranco, Bernabe;Serrano-Gotarredona, Clara;Linares-Barranco, Alejandro;Jimenez-Moreno, Gabriel;Civit-Balcells, Antonio Abad:
A PROGRAMMABLE CONVOLUTION CHIP PROTOTYPE FOR REAL-TIME IMAGE FILTERING. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS DCIS 2005 (20.2005.LISBOA). LISBOA. 2005
A PROGRAMMABLE CONVOLUTION CHIP PROTOTYPE FOR REAL-TIME IMAGE FILTERING. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS DCIS 2005 (20.2005.LISBOA). LISBOA. 2005
Camuñas-Mesa, Luis Alejandro;Acosta-Jimenez, Antonio Jose;Serrano-Gotarredona, Maria Teresa;Linares-Barranco, Bernabe:
ON FULLY DIGITAL ADDRESS-EVENT-REPRESENTATION CONVOLUTION PROCESSING. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS DCIS 2005 (20.2005.LISBOA). LISBOA. 2005
ON FULLY DIGITAL ADDRESS-EVENT-REPRESENTATION CONVOLUTION PROCESSING. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS DCIS 2005 (20.2005.LISBOA). LISBOA. 2005
Parra-Fernández, María Del Pilar;Castro-Ramirez, Javier;Acosta-Jimenez, Antonio Jose:
A METHODOLOGY FOR THE CHARACTERIZATION OF ARITHMETIC CIRCUITS ON CMOS DEEP SUBMICRON TECHNOLOGIES. Comunicación en congreso. CONFERENCE ON VLSI CIRCUITS AND SYSTEMS II (.2005.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2005
A METHODOLOGY FOR THE CHARACTERIZATION OF ARITHMETIC CIRCUITS ON CMOS DEEP SUBMICRON TECHNOLOGIES. Comunicación en congreso. CONFERENCE ON VLSI CIRCUITS AND SYSTEMS II (.2005.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2005
Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose:
PERFORMANCE ANALYSIS OF FULL ADDERS IN CMOS TECHNOLOGIES. Comunicación en congreso. CONFERENCE ON VLSI CIRCUITS AND SYSTEMS II (.2005.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2005
PERFORMANCE ANALYSIS OF FULL ADDERS IN CMOS TECHNOLOGIES. Comunicación en congreso. CONFERENCE ON VLSI CIRCUITS AND SYSTEMS II (.2005.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2005
Camuñas-Mesa, Luis Alejandro;Acosta-Jimenez, Antonio Jose;Serrano-Gotarredona, Maria Teresa;Linares-Barranco, Bernabe:
A DIGITAL PIXEL CELL FOR ADDRESS EVENT REPRESENTATION IMAGE CONVOLUTION PROCESSING. Comunicación en congreso. CONFERENCE ON VLSI CIRCUITS AND SYSTEMS II (.2005.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2005
A DIGITAL PIXEL CELL FOR ADDRESS EVENT REPRESENTATION IMAGE CONVOLUTION PROCESSING. Comunicación en congreso. CONFERENCE ON VLSI CIRCUITS AND SYSTEMS II (.2005.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2005
Serrano-Gotarredona, Rafael;Oster-,Matthias;Wathley-,A. M.;Douglas-,R.;Halfliger-,P;Jiménez-Moreno, G.;Civit-, A;Serrano-Gotarredona, Maria Teresa;Acosta-Jimenez, Antonio Jose;Linares-Barranco, Bernabe;Lichtsteiner-,P.;Linares-Barranco, Alejandro;Paz-Vicente, Rafael;Gómez-Rodríguez, Francisco De Asís;Kolle-Riis,H.;Delbruck-,T.;Liu-,S. C.;Zahnd-,S.:
AER BUILDING BLOCKS FOR MULTI-LAWYER MULTI-CHIP NUEROMORPHIC VISION SYSTEMS. Comunicación en congreso. NIPS 2005: NEURAL INFORMATION PROCESSING SYSTEMS CONFERENCE (.2005.VANCOUVER, CANADA). VANCOUVER, CANADA. 2005
AER BUILDING BLOCKS FOR MULTI-LAWYER MULTI-CHIP NUEROMORPHIC VISION SYSTEMS. Comunicación en congreso. NIPS 2005: NEURAL INFORMATION PROCESSING SYSTEMS CONFERENCE (.2005.VANCOUVER, CANADA). VANCOUVER, CANADA. 2005
Parra-Fernández, María Del Pilar;Castro-Ramirez, Javier;Acosta-Jimenez, Antonio Jose:
APPLICATION OF CLOCK GATING TECHNIQUES AT A FLIP-FLOP LEVEL TO SWITCHING NOISE REDUCTION IN VLSI CIRCUITS. Comunicación en congreso. CONFERENCE ON VLSI CIRCUITS AND SYSTEMS II (.2005.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2005
APPLICATION OF CLOCK GATING TECHNIQUES AT A FLIP-FLOP LEVEL TO SWITCHING NOISE REDUCTION IN VLSI CIRCUITS. Comunicación en congreso. CONFERENCE ON VLSI CIRCUITS AND SYSTEMS II (.2005.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2005
Delgado-Restituto, Manuel;Acosta-Jimenez, Antonio Jose;Rodriguez-Vazquez, Angel:
A MIXED-SIGNAL INTEGRATED CIRCUIT FOR FM-DCSK MODULATION. Comunicación en congreso. 30TH EUROPEAN SOLID-STATE CIRCUIT CONFERENCE (ESSCIRC 2004) () (.2004.LEUVEN, BÉLGICA). LEUVEN, BÉLGICA. 2004
A MIXED-SIGNAL INTEGRATED CIRCUIT FOR FM-DCSK MODULATION. Comunicación en congreso. 30TH EUROPEAN SOLID-STATE CIRCUIT CONFERENCE (ESSCIRC 2004) () (.2004.LEUVEN, BÉLGICA). LEUVEN, BÉLGICA. 2004
Delgado-Restituto, Manuel;Acosta-Jimenez, Antonio Jose;Rodriguez-Vazquez, Angel:
A MIXED-SIGNAL ASIC FOR FM-DCSK MODULATION. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (19.2004.BORDEAUX, FRANCIA). BORDEAUX, FRANCIA. 2004
A MIXED-SIGNAL ASIC FOR FM-DCSK MODULATION. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (19.2004.BORDEAUX, FRANCIA). BORDEAUX, FRANCIA. 2004
Delgado-Restituto, Manuel;Delgado-Restituto, Manuel;Acosta-Jimenez, Antonio Jose;Rodriguez-Vazquez, Angel:
EXPERIMENTAL CHARACTERIZATION OF AN INTEGRATED CHAOS-BASED FMDCSK TRANSMITTER CHIPSET. Comunicación en congreso. 8TH EXPERIMENTAL CHAOS CONFERENCE. FIRENZE, FLORENCIA (ITALIA). 2004
EXPERIMENTAL CHARACTERIZATION OF AN INTEGRATED CHAOS-BASED FMDCSK TRANSMITTER CHIPSET. Comunicación en congreso. 8TH EXPERIMENTAL CHAOS CONFERENCE. FIRENZE, FLORENCIA (ITALIA). 2004
Jimenez-,R;Parra-Fernández, María Del Pilar;Sanmartin-Rodriguez, Pedro Mario;Acosta-Jimenez, Antonio Jose:
A NEW HYBRID CBL-CMOS CELL FOR OPTIMUM NOISE/POWER APPLICATION. Comunicación en congreso. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION WORKSHOP (.2003.DESCONOCIDO). DESCONOCIDO. 2003
A NEW HYBRID CBL-CMOS CELL FOR OPTIMUM NOISE/POWER APPLICATION. Comunicación en congreso. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION WORKSHOP (.2003.DESCONOCIDO). DESCONOCIDO. 2003
Jiménez-Naharro, Raúl;Parra-Fernández, María Del Pilar;Sanmartin-Rodriguez, Pedro Mario;Acosta-Jimenez, Antonio Jose:
OPTIMUM CURRENT/VOLTAGE MODE CIRCUIT PARTITIONING FOR LOW NOISE APPLICATIONS. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (18.2003.CIUDAD REAL, ESPAÑA). CIUDAD REAL, ESPAÑA. 2003
OPTIMUM CURRENT/VOLTAGE MODE CIRCUIT PARTITIONING FOR LOW NOISE APPLICATIONS. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (18.2003.CIUDAD REAL, ESPAÑA). CIUDAD REAL, ESPAÑA. 2003
Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
SWITCHING NOISE REDUCTION IN CLOCK DISTRIBUTION IN MIXED-MODE VLSI CIRCUITS. Comunicación en congreso. PROC. SPIE (.2002.-). -. 2002
SWITCHING NOISE REDUCTION IN CLOCK DISTRIBUTION IN MIXED-MODE VLSI CIRCUITS. Comunicación en congreso. PROC. SPIE (.2002.-). -. 2002
Parra-Fernández, María Del Pilar;Sanmartin-Rodriguez, Pedro Mario;Acosta-Jimenez, Antonio Jose:
ANALYSIS OF CURRENT-MODE FLIP-FLOPS IN CMOS TECHNOLOGIES. Comunicación en congreso. PROC. SPIE (.2002.-). -. 2002
ANALYSIS OF CURRENT-MODE FLIP-FLOPS IN CMOS TECHNOLOGIES. Comunicación en congreso. PROC. SPIE (.2002.-). -. 2002
Parra-Fernández, María Del Pilar;Sanmartin-Rodriguez, Pedro Mario;Acosta-Jimenez, Antonio Jose:
A TECHNIQUE TO GENERATE CMOS VLSI FLIP-FLOP BASED ON DIFFERENTIAL LATCHES. Comunicación en congreso. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION WORKSHOP (.2002.SEVILLA). . 2002
A TECHNIQUE TO GENERATE CMOS VLSI FLIP-FLOP BASED ON DIFFERENTIAL LATCHES. Comunicación en congreso. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION WORKSHOP (.2002.SEVILLA). . 2002
Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
SELECTIVE CLOCK-GATING FOR LOW POWER/LOW NOISE SYNCHRONOUS COUNTERS. Comunicación en congreso. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION WORKSHOP (.2002.SEVILLA). . 2002
SELECTIVE CLOCK-GATING FOR LOW POWER/LOW NOISE SYNCHRONOUS COUNTERS. Comunicación en congreso. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION WORKSHOP (.2002.SEVILLA). . 2002
Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
DESIGN OF SYNCHRONOUS COUNTERS FOR LOW NOISE LOW POWER APPLICATIONS USING CLOCK GATING TECHNIQUES. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (17.2002.SANTANDER, SPAIN). SANTANDER, SPAIN. 2002
DESIGN OF SYNCHRONOUS COUNTERS FOR LOW NOISE LOW POWER APPLICATIONS USING CLOCK GATING TECHNIQUES. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (17.2002.SANTANDER, SPAIN). SANTANDER, SPAIN. 2002
Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose;Jimenez-Fernandez, Carlos Jesus;Valencia-Barrero, Manuel:
A COMPARISON OF SWITCHING NOISE GENERATION IN CMOS BINARY PARALLEL ADDERS. Comunicación en congreso. PROC. DESIGN CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (15.2001.OPORTO). OPORTO. 2001
A COMPARISON OF SWITCHING NOISE GENERATION IN CMOS BINARY PARALLEL ADDERS. Comunicación en congreso. PROC. DESIGN CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (15.2001.OPORTO). OPORTO. 2001
Acosta-Jimenez, Antonio Jose;Parra-Fernández, María Del Pilar;Valencia-Barrero, Manuel:
CHARACTERIZATION AND OPTIMIZED USE OF DIGITAL CMOS LIBRARY CELLS FOR LOW SWITCHING NOISE GENERATION. Comunicación en congreso. PROC. DESIGN CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (15.2001.OPORTO). OPORTO. 2001
CHARACTERIZATION AND OPTIMIZED USE OF DIGITAL CMOS LIBRARY CELLS FOR LOW SWITCHING NOISE GENERATION. Comunicación en congreso. PROC. DESIGN CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (15.2001.OPORTO). OPORTO. 2001
Jiménez-Naharro, Raúl;Parra-Fernández, María Del Pilar;Sanmartín-, P.;Acosta-Jimenez, Antonio Jose:
ANALYSIS OF HIGH-PERFORMANCE FLIP-FLOPS FOR MIXED-SIGNAL APPLICATIONS. Comunicación en congreso. PROC. DESIGN CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (15.2001.OPORTO). OPORTO. 2001
ANALYSIS OF HIGH-PERFORMANCE FLIP-FLOPS FOR MIXED-SIGNAL APPLICATIONS. Comunicación en congreso. PROC. DESIGN CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (15.2001.OPORTO). OPORTO. 2001
Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
REDUCTION OF SWITCHING NOISE IN DIGITAL CMOS CIRCUITS FOR PIN SWAPPING OF LIBRARY CELLS. Comunicación en congreso. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION WORKSHOP (11.2001.YBERDON-LES-BAINS, SUIZA). YBERDON-LES-BAINS, SUIZA. 2001
REDUCTION OF SWITCHING NOISE IN DIGITAL CMOS CIRCUITS FOR PIN SWAPPING OF LIBRARY CELLS. Comunicación en congreso. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION WORKSHOP (11.2001.YBERDON-LES-BAINS, SUIZA). YBERDON-LES-BAINS, SUIZA. 2001
Acosta-Jimenez, Antonio Jose;Parra-Fernández, María Del Pilar;Juan-Chico, Jorge;Valencia-Barrero, Manuel;Jiménez-Naharro, Raúl:
REDUCTION OF SWITCHING NOISE IN LOW-POWER CMOS DIGITAL CIRCUITS BY GATE LEVEL OPTIMIZATION. Comunicación en congreso. INTERNATIONAL WORKSHOP ON LOGIC & SYNTHESIS (10.2001.GRANLIBAKKEN, CALIFORNIA). GRANLIBAKKEN, CALIFORNIA. 2001
REDUCTION OF SWITCHING NOISE IN LOW-POWER CMOS DIGITAL CIRCUITS BY GATE LEVEL OPTIMIZATION. Comunicación en congreso. INTERNATIONAL WORKSHOP ON LOGIC & SYNTHESIS (10.2001.GRANLIBAKKEN, CALIFORNIA). GRANLIBAKKEN, CALIFORNIA. 2001
Bellido-Diaz, Manuel Jesus;Juan-Chico, Jorge;Ruiz De Clavijo-Vazquez, Paulino;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
GATE-LEVEL SIMULATION OF CMOS CIRCUITS USING THE IDDM MODEL. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (33.2001.SYDNEY). SYDNEY. 2001
GATE-LEVEL SIMULATION OF CMOS CIRCUITS USING THE IDDM MODEL. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (33.2001.SYDNEY). SYDNEY. 2001
Martínez-Madrid,M;Peralias-Macias, Eduardo;Acosta-Jimenez, Antonio Jose;Rueda-Rueda, Adoracion:
ANALOG/MIXED SIGNAL IP MODELING FOR DESIGN REUSE. Comunicación en congreso. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE (1.2001.MUNICH). MUNICH. 2001
ANALOG/MIXED SIGNAL IP MODELING FOR DESIGN REUSE. Comunicación en congreso. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE (1.2001.MUNICH). MUNICH. 2001
Ruiz De Clavijo-Vazquez, Paulino;Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
HALOTIS: HIGH ACCURACY LOGIC TIMING SIMULATOR WITH INERTIAL AND DEGRADATION DELAY MODEL. Comunicación en congreso. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE (1.2001.MUNICH). MUNICH. 2001
HALOTIS: HIGH ACCURACY LOGIC TIMING SIMULATOR WITH INERTIAL AND DEGRADATION DELAY MODEL. Comunicación en congreso. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE (1.2001.MUNICH). MUNICH. 2001
Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Ruiz De Clavijo-Vazquez, Paulino;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
GATE-LEVEL MODELING OF THE DELAY DEGRADATION EFFECT. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DCIS 2000 (15.2000.MONTPELLIER, FRANCIA). MONTPELLIER, FRANCIA. 2000
GATE-LEVEL MODELING OF THE DELAY DEGRADATION EFFECT. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DCIS 2000 (15.2000.MONTPELLIER, FRANCIA). MONTPELLIER, FRANCIA. 2000
Jiménez-Naharro, Raúl;Jimenez-, J.;Acosta-Jimenez, Antonio Jose;Peralias-Macias, Eduardo;Rueda-Rueda, Adoracion:
SELF-TIMED IMPLEMENTATION OF THE CODE SYNCRONIZATION AND CORRECTION LOGIC IN A PIPELINED ANALOG TO DIGITAL CONVERTER. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DCIS 2000 (15.2000.MONTPELLIER, FRANCIA). MONTPELLIER, FRANCIA. 2000
SELF-TIMED IMPLEMENTATION OF THE CODE SYNCRONIZATION AND CORRECTION LOGIC IN A PIPELINED ANALOG TO DIGITAL CONVERTER. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DCIS 2000 (15.2000.MONTPELLIER, FRANCIA). MONTPELLIER, FRANCIA. 2000
Verd-,J.;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose:
UN ENTORNO INFORMATICO DE AYUDA A LA DOCENCIA DE SISTEMAS DE COMUNICACION OPTOELECTRONICO. Comunicación en congreso. CONGRESO DE TECNOLOGÍAS APLICADAS A AL ENSEÑANZA DE LA ELECTRÓNICA, TAEE 00 (4.2000.BARCELONA). . 2000
UN ENTORNO INFORMATICO DE AYUDA A LA DOCENCIA DE SISTEMAS DE COMUNICACION OPTOELECTRONICO. Comunicación en congreso. CONGRESO DE TECNOLOGÍAS APLICADAS A AL ENSEÑANZA DE LA ELECTRÓNICA, TAEE 00 (4.2000.BARCELONA). . 2000
Bellido-Diaz, Manuel Jesus;Juan-Chico, Jorge;Ruiz De Clavijo-Vazquez, Paulino;Acosta-Jimenez, Antonio Jose:
CONCEPCION DE UN MICROPROCESADOR: DE LA ESPECIFICACION A LA REALIZACION. Comunicación en congreso. CONGRESO DE TECNOLOGÍAS APLICADAS A AL ENSEÑANZA DE LA ELECTRÓNICA, TAEE 00 (4.2000.BARCELONA). . 2000
CONCEPCION DE UN MICROPROCESADOR: DE LA ESPECIFICACION A LA REALIZACION. Comunicación en congreso. CONGRESO DE TECNOLOGÍAS APLICADAS A AL ENSEÑANZA DE LA ELECTRÓNICA, TAEE 00 (4.2000.BARCELONA). . 2000
Jiménez-Naharro, Raúl;Acosta-Jimenez, Antonio Jose;Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Valencia-Barrero, Manuel:
INFLUENCE OF TIMING SCHEMES ON SWITCHING NOISE GENERATION. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DCIS 2000 (15.2000.MONTPELLIER, FRANCIA). MONTPELLIER, FRANCIA. 2000
INFLUENCE OF TIMING SCHEMES ON SWITCHING NOISE GENERATION. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DCIS 2000 (15.2000.MONTPELLIER, FRANCIA). MONTPELLIER, FRANCIA. 2000
Rodriguez-Vazquez, Angel;Dominguez-Castro, Rafael;Delgado-Restituto, Manuel;Liñan-Cembrano, Gustavo;Rio-Fernandez, Rocio Del;Ceballos-Caceres, Joaquin Francisco;Acosta-Jimenez, Antonio Jose;Ramos-Martos, Juan:
A MIXED-SIGNAL CMOS MODEM ASIC FOR DATA TRANSMISSION ON THE LOW-VOLTAGE POWER-LINE WITH SENSITIVITY OF 283UVRMS AT 10KBPS. Comunicación en congreso. EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (26.2000.ESTOCOLMO). ESTOCOLMO. 2000
A MIXED-SIGNAL CMOS MODEM ASIC FOR DATA TRANSMISSION ON THE LOW-VOLTAGE POWER-LINE WITH SENSITIVITY OF 283UVRMS AT 10KBPS. Comunicación en congreso. EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (26.2000.ESTOCOLMO). ESTOCOLMO. 2000
Juan-Chico, Jorge;Ruiz De Clavijo-Vazquez, Paulino;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
INERTIAL AND DEGRADATION DELAY MODEL FOR CMOS LOGIC GATES. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. GINEBRA, SUIZA. 2000
INERTIAL AND DEGRADATION DELAY MODEL FOR CMOS LOGIC GATES. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. GINEBRA, SUIZA. 2000
Peralias-Macias, Eduardo;Acosta-Jimenez, Antonio Jose;Rueda-,A;Huertas-Diaz, Jose Luis:
A VHDL-BASED METHODOLGY FOR THE DESIGN AND VERIFICATION OF PIPELINE A/D CONVERTERS. Comunicación en congreso. DESIGN, AUTOMATION AND TEST IN EUROPE (1.2000.PARIS). PARIS. 2000
A VHDL-BASED METHODOLGY FOR THE DESIGN AND VERIFICATION OF PIPELINE A/D CONVERTERS. Comunicación en congreso. DESIGN, AUTOMATION AND TEST IN EUROPE (1.2000.PARIS). PARIS. 2000
Acosta-Jimenez, Antonio Jose;Juan-Chico, Jorge;Valencia-Barrero, Manuel:
INFLUENCE OF CLOCKING STRATEGIES ON THE DESIGN OF LOW SWITCHING-NOISE DIGITAL AND MIXED-SIGNAL VLSI CIRCUITS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
INFLUENCE OF CLOCKING STRATEGIES ON THE DESIGN OF LOW SWITCHING-NOISE DIGITAL AND MIXED-SIGNAL VLSI CIRCUITS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
DEGRADATION DELAY MODEL APPLICATION TO OSCILLATORY METASTABILITY. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
DEGRADATION DELAY MODEL APPLICATION TO OSCILLATORY METASTABILITY. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Barriga-Barros, Angel;Valencia-Barrero, Manuel:
CMOS INVERTER INPUT-TO-OUTPUT COUPLING CAPACITANCE MODELLING FOR TIMING ANALYSIS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
CMOS INVERTER INPUT-TO-OUTPUT COUPLING CAPACITANCE MODELLING FOR TIMING ANALYSIS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
Jiménez-Naharro, Raúl;Acosta-Jimenez, Antonio Jose;Bellido-Diaz, Manuel Jesus;Valencia-Barrero, Manuel:
STUDY AND ANALYSIS OF LOW VOLTAGE/LOW POWER CMOS LOGIC FAMILIES FOR LOW SWITCHING NOISE. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
STUDY AND ANALYSIS OF LOW VOLTAGE/LOW POWER CMOS LOGIC FAMILIES FOR LOW SWITCHING NOISE. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
Jiménez-,J.;Acosta-Jimenez, Antonio Jose;Peralias-Macias, Eduardo;Rueda-Rueda, Adoracion:
AN APPLICATION OF SELF-TIMED CIRCUITS TO THE REDUCTION OF SWITCHING NOISE IN ANALOG-DIGITAL CIRCUITS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
AN APPLICATION OF SELF-TIMED CIRCUITS TO THE REDUCTION OF SWITCHING NOISE IN ANALOG-DIGITAL CIRCUITS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
Juan-Chico, Jorge;Ruiz De Clavijo-Vazquez, Paulino;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
DEGRADATION DELAY MODEL EXTENSION TO CMOS GATES. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
DEGRADATION DELAY MODEL EXTENSION TO CMOS GATES. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
Peralias-Macias, Eduardo;Acosta-Jimenez, Antonio Jose;Rueda-Rueda, Adoracion;Huertas-Diaz, Jose Luis:
VHDL MODELS FOR MIXED-SIGNAL DESIGN AND TEST: A CASE STUDY. Comunicación en congreso. ESD-MSD MIXED-SIGNAL TEST WORKSHOP (1.2000.DESCONOCIDO). DESCONOCIDO. 2000
VHDL MODELS FOR MIXED-SIGNAL DESIGN AND TEST: A CASE STUDY. Comunicación en congreso. ESD-MSD MIXED-SIGNAL TEST WORKSHOP (1.2000.DESCONOCIDO). DESCONOCIDO. 2000
Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Barriga-Barros, Angel;Valencia-Barrero, Manuel:
DELAY DEGRADATION EFFECT IN SUBMICRONIC CMOS INVERTERS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
DELAY DEGRADATION EFFECT IN SUBMICRONIC CMOS INVERTERS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (1.2000.KOS, GRECIA). KOS, GRECIA. 2000
Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
LOGIC SIMULATION OF OSCILLATORY METAESTABILITY. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE, DCIS 99 (14.1999.PALMA DE MALLORCA, ESPAÑA). PALMA DE MALLORCA, ESPAÑA. 1999
LOGIC SIMULATION OF OSCILLATORY METAESTABILITY. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE, DCIS 99 (14.1999.PALMA DE MALLORCA, ESPAÑA). PALMA DE MALLORCA, ESPAÑA. 1999
Peralias-Macias, Eduardo;Acosta-Jimenez, Antonio Jose;Rueda-Rueda, Adoracion;Huertas-Diaz, Jose Luis:
A METHODOLOGY FOR USING VHDL DESCRIPTIONS IN MIXED-SIGNAL DESIGN: A PIPELINE ANALOG TO DIGITAL CONVERTERS AS CASE OF STUDY. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (14.1999.PALMA DE MALLORCA). PALMA DE MALLORCA. 1999
A METHODOLOGY FOR USING VHDL DESCRIPTIONS IN MIXED-SIGNAL DESIGN: A PIPELINE ANALOG TO DIGITAL CONVERTERS AS CASE OF STUDY. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (14.1999.PALMA DE MALLORCA). PALMA DE MALLORCA. 1999
Acosta-Jimenez, Antonio Jose;Peralias-Macias, Eduardo;Rueda-Rueda, Adoracion;Huertas-Diaz, Jose Luis:
VHDL BEHAVIOURAL MODELLING OF PIPELINE ANALOG TO DIGITAL CONVERTERS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON ADC MODELLING AND TESTING (1.1999.???). ???. 1999
VHDL BEHAVIOURAL MODELLING OF PIPELINE ANALOG TO DIGITAL CONVERTERS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON ADC MODELLING AND TESTING (1.1999.???). ???. 1999
Acosta-Jimenez, Antonio Jose;Barriga-Barros, Angel;Bellido-Diaz, Manuel Jesus;Valencia-Barrero, Manuel:
SELF-TIMED LINEAR-FEEDBACK SHIFT REGISTERS. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE, DCIS 98 (13.1998.MADRID, ESPAÑA). . 1998
SELF-TIMED LINEAR-FEEDBACK SHIFT REGISTERS. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE, DCIS 98 (13.1998.MADRID, ESPAÑA). . 1998
Parra-Fernández, María Del Pilar;Barriga-Barros, Angel;Acosta-Jimenez, Antonio Jose:
DESARROLLO DE UN ENTORNO INFORMATICO DE AYUDA A LA DOCENCIA DE SISTEMAS DE COMUNICACION. Comunicación en congreso. CONGRESO DE TECNOLOGÍAS APLICADAS A LA ENSEÑANZA DE LA ELECTRÓNICA, TAEE 98 (3.1998.MADRID). . 1998
DESARROLLO DE UN ENTORNO INFORMATICO DE AYUDA A LA DOCENCIA DE SISTEMAS DE COMUNICACION. Comunicación en congreso. CONGRESO DE TECNOLOGÍAS APLICADAS A LA ENSEÑANZA DE LA ELECTRÓNICA, TAEE 98 (3.1998.MADRID). . 1998
Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Barriga-Barros, Angel;Valencia-Barrero, Manuel:
ACCURATE INPUT TO OUTPUT COUPLING CAPACITANCE MODELING FOR DIGITAL CMOS INVERTERS. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE, DCIS 98 (13.1998.MADRID, ESPAÑA). . 1998
ACCURATE INPUT TO OUTPUT COUPLING CAPACITANCE MODELING FOR DIGITAL CMOS INVERTERS. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE, DCIS 98 (13.1998.MADRID, ESPAÑA). . 1998
Acosta-Jimenez, Antonio Jose;Jiménez-Naharro, Raúl;Barriga-Barros, Angel;Bellido-Diaz, Manuel Jesus;Valencia-Barrero, Manuel:
EFFICIENT SELF-TIMED CIRCUITS BASED ON WEAK NMOS-TREES. Comunicación en congreso. INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (1.1998.LISBOA, PORTUGAL). LISBOA, PORTUGAL. 1998
EFFICIENT SELF-TIMED CIRCUITS BASED ON WEAK NMOS-TREES. Comunicación en congreso. INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (1.1998.LISBOA, PORTUGAL). LISBOA, PORTUGAL. 1998
García-,T.A.;Acosta-Jimenez, Antonio Jose;Mora-Gutierrez, Jose Miguel;Ramos-Martos, Juan;Huertas-Diaz, Jose Luis:
A SELF-TIMED BOUNDARY-SCAN ARCHITECTURE FOR MULTI-CHIP MODULE TEST. Comunicación en congreso. MCM TEST ADVANCED TECHNOLOGY WORKSHOP (1.1998.?). ?. 1998
A SELF-TIMED BOUNDARY-SCAN ARCHITECTURE FOR MULTI-CHIP MODULE TEST. Comunicación en congreso. MCM TEST ADVANCED TECHNOLOGY WORKSHOP (1.1998.?). ?. 1998
Rosing-,R.;Kerhoff-,H.;Richardson-,A.M.;Acosta-Jimenez, Antonio Jose:
CLOCK SWITCHING: A NEW DESIGN FOR CURRENT TEST (DCT) METHOD FOR DYNAMIC LOGIC CIRCUITS. Comunicación en congreso. IEEE EUROPEAN TEST WORKSHOP (1.1998.BARCELONA, ESPAÑA). . BARCELONA, ESPAÑA. 1998
CLOCK SWITCHING: A NEW DESIGN FOR CURRENT TEST (DCT) METHOD FOR DYNAMIC LOGIC CIRCUITS. Comunicación en congreso. IEEE EUROPEAN TEST WORKSHOP (1.1998.BARCELONA, ESPAÑA). . BARCELONA, ESPAÑA. 1998
García-,T.A.;Acosta-Jimenez, Antonio Jose;Mora-Gutierrez, Jose Miguel;Ramos-, J.:
A SELF-TIMED SCAN-PATH ARCHITECTURE. Comunicación en congreso. DCIS 97 (.1997.SEVILLA, ESPAÑA). Santander (ESPAÑA). 1997
A SELF-TIMED SCAN-PATH ARCHITECTURE. Comunicación en congreso. DCIS 97 (.1997.SEVILLA, ESPAÑA). Santander (ESPAÑA). 1997
Jiménez-Naharro, Raúl;Acosta-Jimenez, Antonio Jose;Barriga-Barros, Angel;Bellido-Diaz, Manuel Jesus;Valencia-Barrero, Manuel:
PERFORMANCE COMPARISON OF CMOS DIFFERENTIAL CIRCUITS FOR LOW-POWER AND SELF-TIMED APPLICATIONS. Comunicación en congreso. DCIS 97 (.1997.SEVILLA, ESPAÑA). Santander (ESPAÑA). 1997
PERFORMANCE COMPARISON OF CMOS DIFFERENTIAL CIRCUITS FOR LOW-POWER AND SELF-TIMED APPLICATIONS. Comunicación en congreso. DCIS 97 (.1997.SEVILLA, ESPAÑA). Santander (ESPAÑA). 1997
García-,T.A.;Acosta-Jimenez, Antonio Jose;Mora-Gutierrez, Jose Miguel;Ramos-Martos, Juan;Huertas-Diaz, Jose Luis:
A SELF TIMED BOUNDARY SCAN CELLS FOR MULTI-CHIP MODULE TEST. Comunicación en congreso. VLSI TEST SYMPOSIUM (1.1997.MONTEREY, CALIFORNIA (USA)). MONTEREY, CALIFORNIA (USA). 1997
A SELF TIMED BOUNDARY SCAN CELLS FOR MULTI-CHIP MODULE TEST. Comunicación en congreso. VLSI TEST SYMPOSIUM (1.1997.MONTEREY, CALIFORNIA (USA)). MONTEREY, CALIFORNIA (USA). 1997
Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Barriga-Barros, Angel;Valencia-Barrero, Manuel:
FULLY PHYSICAL CHARACTERIZATION OF THE DELAY DEGRADATION EFFECT IN SUBMICRONIC CMOS INVERTERS. Comunicación en congreso. DCIS 97 (.1997.SEVILLA, ESPAÑA). Santander (ESPAÑA). 1997
FULLY PHYSICAL CHARACTERIZATION OF THE DELAY DEGRADATION EFFECT IN SUBMICRONIC CMOS INVERTERS. Comunicación en congreso. DCIS 97 (.1997.SEVILLA, ESPAÑA). Santander (ESPAÑA). 1997
Acosta-Jimenez, Antonio Jose;Bellido-Diaz, Manuel Jesus;Valencia-Barrero, Manuel;Barriga-Barros, Angel;Jiménez-Naharro, Raúl;Huertas-Diaz, Jose Luis:
NEW CMOS VLSI LINEAR SELF-TIMED ARCHITECTURES. Comunicación en congreso. ASYNCHRONOUS DESIGN METHODOLOGIES () (.1996.LONDRES, UK). LONDRES, UK. 1996
NEW CMOS VLSI LINEAR SELF-TIMED ARCHITECTURES. Comunicación en congreso. ASYNCHRONOUS DESIGN METHODOLOGIES () (.1996.LONDRES, UK). LONDRES, UK. 1996
Jimenez-Fernandez, Carlos Jesus;Sanchez-Solano, Santiago;Acosta-Jimenez, Antonio Jose:
METODOLOGÍA DE DISEÑO DE CIRCUITOS INTEGRADOS VLSI. Comunicación en congreso. CONGRESO DE DISEÑO DE CIRCUITOS INTEGRADOS (7.1992.TOLEDO). TOLEDO. 1992
METODOLOGÍA DE DISEÑO DE CIRCUITOS INTEGRADOS VLSI. Comunicación en congreso. CONGRESO DE DISEÑO DE CIRCUITOS INTEGRADOS (7.1992.TOLEDO). TOLEDO. 1992
Acosta-Jimenez, Antonio Jose:
Vulnerability Evaluation and Secure Design Methodology of Cryptohardware for ASIC-embedded Secure Applications to Prevent Side-Channel Attacks. Poster en Congreso. . .
Vulnerability Evaluation and Secure Design Methodology of Cryptohardware for ASIC-embedded Secure Applications to Prevent Side-Channel Attacks. Poster en Congreso. . .
Acosta-Jimenez, Antonio Jose:
Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers. Sesión no plenaria en Congreso. . .
Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers. Sesión no plenaria en Congreso. . .
Artículos publicados
Tena-Sánchez, Erica;Potestad, Francisco Eugenio;Jimenez-Fernandez, Carlos Jesus;Acosta-Jimenez, Antonio Jose;Chaves, Ricardo:
Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks. Applied Sciences. 2022. Vol: 12. Núm: 5. 10.3390/app12052390.
Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks. Applied Sciences. 2022. Vol: 12. Núm: 5. 10.3390/app12052390.
Potestad, Francisco Eugenio;Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose;Jimenez-Fernandez, Carlos Jesus;Chaves, Ricardo:
Hardware Countermeasures Benchmarking against Fault Attacks. Applied Sciences. 2022. Vol: 12. Núm: 5. 10.3390/app12052443.
Hardware Countermeasures Benchmarking against Fault Attacks. Applied Sciences. 2022. Vol: 12. Núm: 5. 10.3390/app12052443.
Potestad, Francisco Eugenio;Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose;Jimenez-Fernandez, Carlos Jesus;Chaves, Ricardo:
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. IEEE Access. 2022. Vol: 10. Pág. 65548-65561. 10.1109/ACCESS.2022.3183764.
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. IEEE Access. 2022. Vol: 10. Pág. 65548-65561. 10.1109/ACCESS.2022.3183764.
Delgado -lozano, Ignacio M;Acosta-Jimenez, Antonio Jose;Tena-Sánchez, Erica;Nuñez-Martínez, Juan:
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. IEEE Embedded Systems Letters. 2022. Vol: 14. Núm: 2. Pág. 99-102. 10.1109/LES.2021.3122395.
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. IEEE Embedded Systems Letters. 2022. Vol: 14. Núm: 2. Pág. 99-102. 10.1109/LES.2021.3122395.
Delgado-lozano, I. M.;Tena-Sánchez, Erica;Nuñez-Martínez, Juan;Acosta-Jimenez, Antonio Jose:
Projection of dual-rail DPA countermeasures in future FinFET and emerging TFET technologies. ACM Journal on Emerging Technologies in Computing Systems. 2020. Vol: 16. Núm: 3. Pág. 1-16. 10.1145/3381857.
Projection of dual-rail DPA countermeasures in future FinFET and emerging TFET technologies. ACM Journal on Emerging Technologies in Computing Systems. 2020. Vol: 16. Núm: 3. Pág. 1-16. 10.1145/3381857.
Delgado-lozano, Ignacio M.;Tena-Sánchez, Erica;Nuñez-Martínez, Juan;Acosta-Jimenez, Antonio Jose:
Design and analysis of secure emerging crypto-hardware using HyperFET devices. IEEE Transactions on Emerging Topics in Computing. 2020. Vol: Online. 10.1109/TETC.2020.2977735.
Design and analysis of secure emerging crypto-hardware using HyperFET devices. IEEE Transactions on Emerging Topics in Computing. 2020. Vol: Online. 10.1109/TETC.2020.2977735.
Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose:
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks. International Journal of Circuit Theory and Applications. 2019. Vol: 47. Núm: 2. Pág. 238-253.
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks. International Journal of Circuit Theory and Applications. 2019. Vol: 47. Núm: 2. Pág. 238-253.
Acosta-Jimenez, Antonio Jose;Addabbo, Tommaso;Tena-Sánchez, Erica:
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview. International Journal of Circuit Theory and Applications. 2017. Vol: 45. Núm: 2. Pág. 145-167. 10.1002/cta.2296.
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview. International Journal of Circuit Theory and Applications. 2017. Vol: 45. Núm: 2. Pág. 145-167. 10.1002/cta.2296.
Acosta-Jimenez, Antonio Jose;Tena-Sánchez, Erica;Jimenez-Fernandez, Carlos Jesus;Mora-Gutierrez, Jose Miguel:
Power and Energy Issues on Lightweight Cryptography. Journal of low power electronics. 2017. Vol: 13. Núm: 3. Pág. 326-337. 10.1166/jolpe.2017.1490.
Power and Energy Issues on Lightweight Cryptography. Journal of low power electronics. 2017. Vol: 13. Núm: 3. Pág. 326-337. 10.1166/jolpe.2017.1490.
Acosta-Jimenez, Antonio Jose;Addabbo, Tommaso:
Guest Editorial 'Secure lightweight crypto-hardware'. International Journal of Circuit Theory and Applications. 2017. Vol: 45. Núm: 2. Pág. 143-144. 10.1002/cta.2302.
Guest Editorial 'Secure lightweight crypto-hardware'. International Journal of Circuit Theory and Applications. 2017. Vol: 45. Núm: 2. Pág. 143-144. 10.1002/cta.2302.
Brox-Jimenez, Piedad;Martínez-Rodríguez, Macarena Cristina;Tena-Sánchez, Erica;Baturone-Castillo, Iluminada;Acosta-Jimenez, Antonio Jose:
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions. International Journal of Circuit Theory and Applications. 2016. Vol: 44. Núm: 1. Pág. 4-20. 10.1002/cta.2058.
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions. International Journal of Circuit Theory and Applications. 2016. Vol: 44. Núm: 1. Pág. 4-20. 10.1002/cta.2058.
Tena-Sánchez, Erica;Castro-Ramirez, Javier;Acosta-Jimenez, Antonio Jose:
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2014. Vol: 4. Núm: 2. Pág. 203-215. 10.1109/JETCAS.2014.2315878.
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2014. Vol: 4. Núm: 2. Pág. 203-215. 10.1109/JETCAS.2014.2315878.
Castro-Ramirez, Javier;Acosta-Jimenez, Antonio Jose:
Automatic and systematic control of experimental data measurements on ASICs. Instrumentation ViewPoint. 2013. Núm: 14. Pág. 45-45.
Automatic and systematic control of experimental data measurements on ASICs. Instrumentation ViewPoint. 2013. Núm: 14. Pág. 45-45.
Brox-Jimenez, Piedad;Castro-Ramirez, Javier;Martínez-Rodríguez, Macarena Cristina;Tena-Sánchez, Erica;Jimenez-Fernandez, Carlos Jesus;Baturone-Castillo, Iluminada;Acosta-Jimenez, Antonio Jose:
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 2013. Vol: 60. Núm: 12. Pág. 3182-3194. 10.1109/TCSI.2013.2265962.
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 2013. Vol: 60. Núm: 12. Pág. 3182-3194. 10.1109/TCSI.2013.2265962.
Camuñas-Mesa, Luis Alejandro;Zamarreño-Ramos, Carlos;Linares-Barranco, Alejandro;Acosta-Jimenez, Antonio Jose;Serrano-Gotarredona, Maria Teresa;Linares-Barranco, Bernabe:
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors. IEEE Journal of Solid-State Circuits. 2012. Vol: 47. Núm: 2. Pág. 504-517. 10.1109/JSSC.2011.2167409 .
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors. IEEE Journal of Solid-State Circuits. 2012. Vol: 47. Núm: 2. Pág. 504-517. 10.1109/JSSC.2011.2167409 .
Serrano-Gotarredona, Maria Teresa;Acosta-Jimenez, Antonio Jose;Camuñas-Mesa, Luis Alejandro;Linares-Barranco, Bernabe;Zamarreño-Ramos, Carlos:
A 32 32 PIXEL CONVOLUTION PROCESSOR CHIP FOR ADDRESS EVENT VISION SENSORS WITH 155 NS EVENT LATENCY AND 20 MEPS THROUGHPUT. IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 2010. Vol: 58. Núm: 4. Pág. 777-790.
A 32 32 PIXEL CONVOLUTION PROCESSOR CHIP FOR ADDRESS EVENT VISION SENSORS WITH 155 NS EVENT LATENCY AND 20 MEPS THROUGHPUT. IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 2010. Vol: 58. Núm: 4. Pág. 777-790.
Castro-Ramirez, Javier;Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose:
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. Lecture Notes in Computer Science. 2009. Vol: 5953. Pág. 76-85. 10.1007/978-3-642-11802-9_12.
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. Lecture Notes in Computer Science. 2009. Vol: 5953. Pág. 76-85. 10.1007/978-3-642-11802-9_12.
Serrano-Gotarredona, Rafael;Oster-,Matthias;Liu-,S. C.;Douglas-,R.;Hafliger-,Philip;Jimenez-Moreno, Gabriel;Civit-Balcells, Antonio Abad;Serrano-Gotarredona, Maria Teresa;Acosta-Jimenez, Antonio Jose;Linares-Barranco, Bernabe;Lichtsteiner-,P.;Linares-Barranco, Alejandro;Paz-Vicente, Rafael;Gómez-Rodríguez, Francisco De Asís;Camuñas-Mesa, Luis Alejandro;Berner-,Raphael;Rivas-Pérez, Manuel;Delbruck-,T.:
CAVIAR: A 45K NEURON, 5M SYNAPSE, 12G CONNECTS/S AER HARDWARE SENSORY-PROCESSING- LEARNING-ACTUATING SYSTEM FOR HIGH-SPEED VISUAL OBJECT RECOGNITION A. IEEE Transactions on Neural Networks. 2009. Vol: 20. Núm: 9. Pág. 1417-1438.
CAVIAR: A 45K NEURON, 5M SYNAPSE, 12G CONNECTS/S AER HARDWARE SENSORY-PROCESSING- LEARNING-ACTUATING SYSTEM FOR HIGH-SPEED VISUAL OBJECT RECOGNITION A. IEEE Transactions on Neural Networks. 2009. Vol: 20. Núm: 9. Pág. 1417-1438.
Serrano-Gotarredona, Rafael;Serrano-Gotarredona, Maria Teresa;Acosta-Jimenez, Antonio Jose;Serrano-Gotarredona, Clara;Pérez-Carrasco, Jose Antonio;Linares-Barranco, Bernabe;Linares-Barranco, Alejandro;Jimenez-Moreno, Gabriel;Civit-Balcells, Antonio Abad:
ON REAL-TIME AER 2-D CONVOLUTIONS HARDWARE FOR NEUROMORPHIC SPIKE-BASED CORTICAL PROCESSING. IEEE Transactions on Neural Networks. 2008. Vol: 19. Núm: 7. Pág. 1196-1219.
ON REAL-TIME AER 2-D CONVOLUTIONS HARDWARE FOR NEUROMORPHIC SPIKE-BASED CORTICAL PROCESSING. IEEE Transactions on Neural Networks. 2008. Vol: 19. Núm: 7. Pág. 1196-1219.
Serrano-Gotarredona, Rafael;Serrano-Gotarredona, Maria Teresa;Acosta-Jimenez, Antonio Jose;Linares-Barranco, Bernabe:
A NEUROMORPHIC CORTICAL-LAYER MICROCHIP FOR SPIKE-BASED EVENT PROCESSING VISSION SYSTEMS. IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2006. Vol: 53. Núm: 12. Pág. 2548-2566.
A NEUROMORPHIC CORTICAL-LAYER MICROCHIP FOR SPIKE-BASED EVENT PROCESSING VISSION SYSTEMS. IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2006. Vol: 53. Núm: 12. Pág. 2548-2566.
Jiménez-Naharro, Raúl;Parra-Fernández, María Del Pilar;Castro-Ramirez, Javier;Sánchez-Raya, Manuel;Acosta-Jimenez, Antonio Jose:
OPTIMIZATION OF MASTER-SLAVE FLIP-FLOPS FOR HIGH-PERFORMANCE APPLICATIONS. Lecture Notes in Computer Science. 2006. Vol: 4148. Pág. 439-449.
OPTIMIZATION OF MASTER-SLAVE FLIP-FLOPS FOR HIGH-PERFORMANCE APPLICATIONS. Lecture Notes in Computer Science. 2006. Vol: 4148. Pág. 439-449.
Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose;Jiménez-Naharro, Raúl;Valencia-Barrero, Manuel:
SELECTIVE CLOCK-GATING FOR LOW-POWER SYNCHRONOUS COUNTERS. Journal of low power electronics. 2005. Vol: 1. Núm: 1. Pág. 11-19.
SELECTIVE CLOCK-GATING FOR LOW-POWER SYNCHRONOUS COUNTERS. Journal of low power electronics. 2005. Vol: 1. Núm: 1. Pág. 11-19.
Delgado-Restituto, Manuel;Acosta-Jimenez, Antonio Jose;Rodriguez-Vazquez, Angel:
A MIXED-SIGNAL INTEGRATED CIRCUIT FOR FM-DCSK MODULATION. IEEE Journal of Solid-State Circuits. 2005. Vol: 40. Núm: 7. Pág. 1460-1471.
A MIXED-SIGNAL INTEGRATED CIRCUIT FOR FM-DCSK MODULATION. IEEE Journal of Solid-State Circuits. 2005. Vol: 40. Núm: 7. Pág. 1460-1471.
Parra-Fernández, María Del Pilar;Castro-Ramirez, Javier;Valencia-Barrero, Manuel;Acosta-Jimenez, Antonio Jose:
Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits. Proceedings of SPIE: The International Society for Optical Engineering. 2005. Vol: 5837. Pág. 1003-1014 . 10.1117/12.608276.
Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits. Proceedings of SPIE: The International Society for Optical Engineering. 2005. Vol: 5837. Pág. 1003-1014 . 10.1117/12.608276.
Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
SWITCHING NOISE REDUCTION IN CLOCK DISTRIBUTION IN MIXED-MODE VLSI CIRCUITS. Progress in Biomedical Optics and Imaging. 2003. Vol: 5117. Pág. 564-573.
SWITCHING NOISE REDUCTION IN CLOCK DISTRIBUTION IN MIXED-MODE VLSI CIRCUITS. Progress in Biomedical Optics and Imaging. 2003. Vol: 5117. Pág. 564-573.
Jiménez-Naharro, Raúl;Parra-Fernández, María Del Pilar;Sanmartin-Rodriguez, Pedro Mario;Acosta-Jimenez, Antonio Jose:
A NEW HYBRID CBL-CMOS CELL FOR OPTIMUM NOISE/POWER APPLICATIONS. Lecture Notes in Computer Science. 2003. Núm: 2799. Pág. 491-500.
A NEW HYBRID CBL-CMOS CELL FOR OPTIMUM NOISE/POWER APPLICATIONS. Lecture Notes in Computer Science. 2003. Núm: 2799. Pág. 491-500.
Jiménez-Naharro, Raúl;Parra-Fernández, María Del Pilar;Sanmartin-Rodriguez, Pedro Mario;Acosta-Jimenez, Antonio Jose:
ANALYSIS OF CURRENT-MODE FLIP-FLOPS IN CMOS TECHNOLOGIES. Progress in Biomedical Optics and Imaging. 2003. Vol: 5117. Pág. 515-526.
ANALYSIS OF CURRENT-MODE FLIP-FLOPS IN CMOS TECHNOLOGIES. Progress in Biomedical Optics and Imaging. 2003. Vol: 5117. Pág. 515-526.
Jiménez-Naharro, Raúl;Parra-Fernández, María Del Pilar;Sanmartin-Rodriguez, Pedro Mario;Acosta-Jimenez, Antonio Jose:
HIGH-PERFORMANCE EDGE-TRIGGERED FLIP-FLOPS USING WEAK-BRANCH DIFFERENTIAL LATCH. Electronics Letters. 2002. Vol: 38. Núm: 21. Pág. 1243-1244.
HIGH-PERFORMANCE EDGE-TRIGGERED FLIP-FLOPS USING WEAK-BRANCH DIFFERENTIAL LATCH. Electronics Letters. 2002. Vol: 38. Núm: 21. Pág. 1243-1244.
Parra-Fernández, María Del Pilar;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
SELECTIVE CLOCK-GATING FOR LOW POWER/LOW NOISE SYNCHRONOUS COUNTERS. Lecture Notes in Computer Science. 2002. Vol: 2451. Pág. 448-457.
SELECTIVE CLOCK-GATING FOR LOW POWER/LOW NOISE SYNCHRONOUS COUNTERS. Lecture Notes in Computer Science. 2002. Vol: 2451. Pág. 448-457.
Jiménez-Naharro, Raúl;Parra-Fernández, María Del Pilar;Sanmartin-Rodriguez, Pedro Mario;Acosta-Jimenez, Antonio Jose:
ANALYSIS OF HIGH-PERFORMANCE FLIP-FLOPS FOR SUBMICRON MIXED-SIGNAL APPLICATIONS. Analog Integrated Circuits and Signal Processing. 2002. Vol: 33. Núm: 2. Pág. 145-156.
ANALYSIS OF HIGH-PERFORMANCE FLIP-FLOPS FOR SUBMICRON MIXED-SIGNAL APPLICATIONS. Analog Integrated Circuits and Signal Processing. 2002. Vol: 33. Núm: 2. Pág. 145-156.
Acosta-Jimenez, Antonio Jose;Peralias-Macias, Eduardo;Huertas-Diaz, Jose Luis;Rueda-,A:
VHDL BEHAVIOURAL MODELLING OF PIPELINE ANALOG TO DIGITAL CONVERTERS. Measurement: Journal of the International Measurement Confederation. 2002. Vol: 31. Núm: 1. Pág. 47-60.
VHDL BEHAVIOURAL MODELLING OF PIPELINE ANALOG TO DIGITAL CONVERTERS. Measurement: Journal of the International Measurement Confederation. 2002. Vol: 31. Núm: 1. Pág. 47-60.
Jiménez-Naharro, Raúl;Parra-Fernández, María Del Pilar;Sanmartin-Rodriguez, Pedro Mario;Acosta-Jimenez, Antonio Jose:
A TECHNIQUE TO GENERATE CMOS VLSI FLIP-FLOPS BASED ON DIFFERENTIAL LATCHES. Lecture Notes in Computer Science. 2002. Vol: 2451. Pág. 209-218.
A TECHNIQUE TO GENERATE CMOS VLSI FLIP-FLOPS BASED ON DIFFERENTIAL LATCHES. Lecture Notes in Computer Science. 2002. Vol: 2451. Pág. 209-218.
Jiménez-Naharro, Raúl;Acosta-Jimenez, Antonio Jose;Peralias-Macias, Eduardo;Rueda-,A:
AN APPLICATION OF SELF-TIMED CIRCUITS TO THE REDUCTION OF SWITCHING NOISE IN ANALOG-DIGITAL CIRCUITS. Lecture Notes in Computer Science. 2000. Vol: 1918. Pág. 295-305.
AN APPLICATION OF SELF-TIMED CIRCUITS TO THE REDUCTION OF SWITCHING NOISE IN ANALOG-DIGITAL CIRCUITS. Lecture Notes in Computer Science. 2000. Vol: 1918. Pág. 295-305.
Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Ruiz De Clavijo-Vazquez, Paulino;Valencia-Barrero, Manuel:
DEGRADATION DELAY MODEL EXTENSION TO CMOS GATES. Lecture Notes in Computer Science. 2000. Vol: 1918. Pág. 149-158.
DEGRADATION DELAY MODEL EXTENSION TO CMOS GATES. Lecture Notes in Computer Science. 2000. Vol: 1918. Pág. 149-158.
Acosta-Jimenez, Antonio Jose;Jiménez-Naharro, Raúl;Juan-Chico, Jorge;Bellido-Diaz, Manuel Jesus;Valencia-Barrero, Manuel:
INFLUENCE OF CLOCKING STRATEGIES ON THE DESIGN OF LOW SWITCHING-NOISE DIGITAL AND MIXED-SIGNAL VLSI CIRCUITS. Lecture Notes in Computer Science. 2000. Vol: 1918. Pág. 316-326.
INFLUENCE OF CLOCKING STRATEGIES ON THE DESIGN OF LOW SWITCHING-NOISE DIGITAL AND MIXED-SIGNAL VLSI CIRCUITS. Lecture Notes in Computer Science. 2000. Vol: 1918. Pág. 316-326.
Bellido-Diaz, Manuel Jesus;Juan-Chico, Jorge;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel;Huertas-Diaz, Jose Luis:
LOGICAL MODELLING OF DELAY DEGRADATION EFFECT IN STATIC CMOS GATES. IEE Proceedings. Circuits, Devices and Systems. 2000. Vol: 147. Núm: 2. Pág. 107-117.
LOGICAL MODELLING OF DELAY DEGRADATION EFFECT IN STATIC CMOS GATES. IEE Proceedings. Circuits, Devices and Systems. 2000. Vol: 147. Núm: 2. Pág. 107-117.
Bellido-Diaz, Manuel Jesus;Juan-Chico, Jorge;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel:
INERTIAL EFFECT HANDLING METHOD FOR CMOS DIGITAL IC SIMULATION. Electronics Letters. 1999. Vol: 35. Núm: 23. Pág. 2028-2030.
INERTIAL EFFECT HANDLING METHOD FOR CMOS DIGITAL IC SIMULATION. Electronics Letters. 1999. Vol: 35. Núm: 23. Pág. 2028-2030.
Acosta-Jimenez, Antonio Jose;Mora-Gutierrez, Jose Miguel:
SELF-TIMED BOUNDARY-SCAN CELLS FOR MULTI-CHIP MODULE TEST. Journal of Electronic Testing. 1999. Vol: 15. Núm: 1-2. Pág. 115-127.
SELF-TIMED BOUNDARY-SCAN CELLS FOR MULTI-CHIP MODULE TEST. Journal of Electronic Testing. 1999. Vol: 15. Núm: 1-2. Pág. 115-127.
Acosta-Jimenez, Antonio Jose;Jiménez-Naharro, Raúl;Barriga-Barros, Angel;Bellido-Diaz, Manuel Jesus;Valencia-Barrero, Manuel;Huertas-Diaz, Jose Luis:
DESIGN AND CHARACTERISATION OF A CMOS VLSI SELF-TIMED MULTIPLIER ARCHITECTURE BASED ON A BIT-LEVEL PIPELINED-ARRAY STRUCTURE. IEE Proceedings. Circuits, Devices and Systems. 1998. Vol: 145. Núm: 4. Pág. 247-253.
DESIGN AND CHARACTERISATION OF A CMOS VLSI SELF-TIMED MULTIPLIER ARCHITECTURE BASED ON A BIT-LEVEL PIPELINED-ARRAY STRUCTURE. IEE Proceedings. Circuits, Devices and Systems. 1998. Vol: 145. Núm: 4. Pág. 247-253.
Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel;Juan-Chico, Jorge:
ANALYSIS OF METASTABLE OPERATION IN A CMOS DYNAMIC D-LATCH. Analog Integrated Circuits and Signal Processing. 1997. Vol: 14. Núm: 1-2. Pág. 143-157.
ANALYSIS OF METASTABLE OPERATION IN A CMOS DYNAMIC D-LATCH. Analog Integrated Circuits and Signal Processing. 1997. Vol: 14. Núm: 1-2. Pág. 143-157.
Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Juan-Chico, Jorge;Barriga-Barros, Angel;Valencia-Barrero, Manuel:
CMOS INVERTER MAXIMUM FREQUENCY OF OPERATION DUE TO DIGITAL SIGNAL DEGRADATION. Electronics Letters. 1997. Vol: 33. Núm: 19. Pág. 1619-1621.
CMOS INVERTER MAXIMUM FREQUENCY OF OPERATION DUE TO DIGITAL SIGNAL DEGRADATION. Electronics Letters. 1997. Vol: 33. Núm: 19. Pág. 1619-1621.
Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Luque-Rodríguez, Joaquín;Barriga-Barros, Angel;Valencia-Barrero, Manuel:
EVALUATION OF METASTABILITY TRANSFER MODELS - AN APPLICATION TO AN N-BISTABLE CMOS SYNCHRONIZER. International Journal of Electronics. 1995. Vol: 79. Núm: 5. Pág. 585-593.
EVALUATION OF METASTABILITY TRANSFER MODELS - AN APPLICATION TO AN N-BISTABLE CMOS SYNCHRONIZER. International Journal of Electronics. 1995. Vol: 79. Núm: 5. Pág. 585-593.
Valencia-Barrero, Manuel;Bellido-Diaz, Manuel Jesus;Huertas-Diaz, Jose Luis;Acosta-Jimenez, Antonio Jose;Sanchez-Solano, Santiago:
MODULAR ASYNCHRONOUS ARBITER INSENSITIVE TO METASTABILITY. IEEE Transactions on Computers. 1995. Vol: 44. Núm: 12. Pág. 1456-1461.
MODULAR ASYNCHRONOUS ARBITER INSENSITIVE TO METASTABILITY. IEEE Transactions on Computers. 1995. Vol: 44. Núm: 12. Pág. 1456-1461.
Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel;Barriga-Barros, Angel;Bellido-Diaz, Manuel Jesus;Huertas-Diaz, Jose Luis:
SODS - A NEW CMOS DIFFERENTIAL-TYPE STRUCTURE. IEEE Journal of Solid-State Circuits. 1995. Vol: 30. Núm: 7. Pág. 835-838.
SODS - A NEW CMOS DIFFERENTIAL-TYPE STRUCTURE. IEEE Journal of Solid-State Circuits. 1995. Vol: 30. Núm: 7. Pág. 835-838.
Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel;Barriga-Barros, Angel;Bellido-Diaz, Manuel Jesus;Huertas-Diaz, Jose Luis:
DESIGN, TESTING AND APPLICATIONS OF 4-VALUED PADS. International Journal of Electronics. 1993. Vol: 75. Núm: 1. Pág. 115-131.
DESIGN, TESTING AND APPLICATIONS OF 4-VALUED PADS. International Journal of Electronics. 1993. Vol: 75. Núm: 1. Pág. 115-131.
Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel;Barriga-Barros, Angel;Huertas-Diaz, Jose Luis;Bellido-Diaz, Manuel Jesus:
MULTIPLE-VALUED PADS FOR BINARY CHIPS. Electronics Letters. 1992. Vol: 28. Núm: 8. Pág. 794-796.
MULTIPLE-VALUED PADS FOR BINARY CHIPS. Electronics Letters. 1992. Vol: 28. Núm: 8. Pág. 794-796.
Bellido-Diaz, Manuel Jesus;Acosta-Jimenez, Antonio Jose;Valencia-Barrero, Manuel;Barriga-Barros, Angel;Huertas-Diaz, Jose Luis:
SIMPLE BINARY RANDOM NUMBER GENERATOR. Electronics Letters. 1992. Vol: 28. Núm: 7. Pág. 617-618.
SIMPLE BINARY RANDOM NUMBER GENERATOR. Electronics Letters. 1992. Vol: 28. Núm: 7. Pág. 617-618.
Patentes
Acosta-Jimenez, Antonio Jose;Baturone-Castillo, Iluminada;Castro-Ramirez, Javier;Jimenez-Fernandez, Carlos Jesus;Martínez-Rodríguez, Macarena Cristina: Method for generating piecwise-affine multivariable functions with on-line computation of the search tree and device for implementing same. Número de patente: ES245815B1
Acosta-Jimenez, Antonio Jose;Baturone-Castillo, Iluminada;Castro-Ramirez, Javier;Jimenez-Fernandez, Carlos Jesus;Brox-Jimenez, Piedad;Martínez-Rodríguez, Macarena Cristina: Método para generar funciones multivariables afines a tramos con computación on-line del árbol de búsqueda y dispositivo para implementación del métod. Número de patente: P201200608
Brox-Jimenez, Piedad;Martínez-Rodríguez, Macarena Cristina;Baturone-Castillo, Iluminada;Acosta-Jimenez, Antonio Jose;Castro-Ramirez, Javier: Método y dispositivo para generar identificadores y números verdaderamente aleatorios. Número de patente: PCT/ES2014/000131
Tesis dirigidas o codirigidas
Castro-Ramirez, Javier:
Desarrollo y aplicaciones de técnicas de control de corriente de alimentación en circuitos integrados digitales CMOS. Tesis Doctoral. 2011
Desarrollo y aplicaciones de técnicas de control de corriente de alimentación en circuitos integrados digitales CMOS. Tesis Doctoral. 2011
Parra-Fernández, María Del Pilar:
Ruido de conmutación en circuitos integrados digitales CMOS. Tesis Doctoral. 2010
Ruido de conmutación en circuitos integrados digitales CMOS. Tesis Doctoral. 2010
Camuñas-Mesa, Luis Alejandro:
MICROCHIPS CONVOLUCIONADORES AER PARA PROCESADO ASÍNCRONO NEOCORTICAL DE INFORMACIÓN SENSORIAL VISUAL CODIFICADA EN EVENTOS. Tesis Doctoral. 2010
MICROCHIPS CONVOLUCIONADORES AER PARA PROCESADO ASÍNCRONO NEOCORTICAL DE INFORMACIÓN SENSORIAL VISUAL CODIFICADA EN EVENTOS. Tesis Doctoral. 2010
Jiménez-Naharro, Raúl:
UNA APORTACION AL DISEÑO DE CIRCUITOS INTEGRADOS CMOS AUTOTEMPORIZADOS. Tesis Doctoral. 2000
UNA APORTACION AL DISEÑO DE CIRCUITOS INTEGRADOS CMOS AUTOTEMPORIZADOS. Tesis Doctoral. 2000
