Directorio
FRANCISCO EUGENIO POTESTAD ORDOÑEZ
Categoría
Profesor Ayudante Doctor
Contacto
Correo electrónico
Departamento
Área
Tecnología Electrónica
Docencia
Investigación
Grupo de investigación
DISEÑO DE CIRCUITOS INTEGRADOS DIGITALES Y MIXTOS (DISEÑO DE CIRCUITOS INTEGRADOS)
Proyectos y contratos de investigación
Integración y Validación en Laboratorio de Contramedidas Frente a Ataques Laterales en Criptocircuitos Microelectrónicos (TEC2016-80549-R - Investigador/a)
Cesar: Circuitos Microelectrónicos Seguros Frente a Ataques Laterales (TEC2013-45523-R - Investigador/a)
Capítulos en Libros
Tena-Sánchez, Erica;Potestad, Francisco Eugenio;Parra-Fernández, María Del Pilar;Baena-Oliva, Maria Carmen;Valencia-Barrero, Manuel;Jimenez-Fernandez, Carlos Jesus;Acosta-Jimenez, Antonio Jose:
DESIGN AND SECURITY EVALUATION OF SECURE CRYPTOHARDWARE (FPGA AND ASIC) AGAINST HACKERS EXPLOITING SIDE-CHANNEL INFORMATION DESIGN AND SECURITY EVALUA. Pág. 47-50. 3ciencias (www.3ciencias.com). 3ciencias (www.3ciencias.com). 2022.
DESIGN AND SECURITY EVALUATION OF SECURE CRYPTOHARDWARE (FPGA AND ASIC) AGAINST HACKERS EXPLOITING SIDE-CHANNEL INFORMATION DESIGN AND SECURITY EVALUA. Pág. 47-50. 3ciencias (www.3ciencias.com). 3ciencias (www.3ciencias.com). 2022.
Asistencia a congresos
Potestad, Francisco Eugenio;Jimenez-Fernandez, Carlos Jesus;Gallardo, Alejandro;Valencia-Barrero, Manuel;Baena-Oliva, Maria Carmen;Parra-Fernández, María Del Pilar;Tena-Sánchez, Erica:
ICs tester design and its effect on application in electronics laboratories. Comunicación en congreso. 2022 Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (XV Technologies Applied to Electronics Teaching Conference). Escuela Universitaria Politecnica, Universidad de Zaragoza, Teruel. 2022
ICs tester design and its effect on application in electronics laboratories. Comunicación en congreso. 2022 Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (XV Technologies Applied to Electronics Teaching Conference). Escuela Universitaria Politecnica, Universidad de Zaragoza, Teruel. 2022
Jimenez-Fernandez, Carlos Jesus;Baena-Oliva, Maria Carmen;Parra-Fernández, María Del Pilar;Valencia-Barrero, Manuel;Potestad, Francisco Eugenio;Tena-Sánchez, Erica;Gallardo, Alejandro:
Teaching based on proposed by students designs: a case study. Comunicación en congreso. 2022 Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (XV Technologies Applied to Electronics Teaching Conference). Escuela Universitaria Politecnica, Universidad de Zaragoza, Teruel. 2022
Teaching based on proposed by students designs: a case study. Comunicación en congreso. 2022 Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (XV Technologies Applied to Electronics Teaching Conference). Escuela Universitaria Politecnica, Universidad de Zaragoza, Teruel. 2022
Jimenez-Fernandez, Carlos Jesus;Baena-Oliva, Maria Carmen;Parra-Fernández, María Del Pilar;Gallardo, Alejandro;Potestad, Francisco Eugenio;Valencia-Barrero, Manuel:
Learning VHDL through teamwork FPGA game design. Ponencia en Congreso. 2020 XIV Technologies Applied to Electronics Teaching Conference (TAEE). - Oporto, Portugal. 2020
Learning VHDL through teamwork FPGA game design. Ponencia en Congreso. 2020 XIV Technologies Applied to Electronics Teaching Conference (TAEE). - Oporto, Portugal. 2020
Potestad, Francisco Eugenio;Tena-Sánchez, Erica;Chaves, Ricardo;Valencia-Barrero, Manuel;Acosta-Jimenez, Antonio Jose;Jimenez-Fernandez, Carlos Jesus:
Hamming-code based fault detection desing methodology for block ciphers. Ponencia en Congreso. IEEE International Symposium on Circuits and Systems (ISCAS). , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Facultad de Ciencias Económicas y Empresariales. Universidad de Sevilla. 2020
Hamming-code based fault detection desing methodology for block ciphers. Ponencia en Congreso. IEEE International Symposium on Circuits and Systems (ISCAS). , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Facultad de Ciencias Económicas y Empresariales. Universidad de Sevilla. 2020
Potestad, Francisco Eugenio;Jimenez-Fernandez, Carlos Jesus;Valencia-Barrero, Manuel;Baena-Oliva, Maria Carmen;Parra-Fernández, María Del Pilar:
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. Comunicación en congreso. XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS 2018). Lyon, France. 2018
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. Comunicación en congreso. XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS 2018). Lyon, France. 2018
Potestad, Francisco Eugenio;Jimenez-Fernandez, Carlos Jesus;Valencia-Barrero, Manuel;Baena-Oliva, Maria Carmen;Parra-Fernández, María Del Pilar:
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. Comunicación en congreso. XXXIII CONFERENCE ON DESIGN OF CIRCUITSAND INTEGRATED SYSTEMS (DCIS 2018). Lyon, France. 2018
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. Comunicación en congreso. XXXIII CONFERENCE ON DESIGN OF CIRCUITSAND INTEGRATED SYSTEMS (DCIS 2018). Lyon, France. 2018
Jimenez-Fernandez, Carlos Jesus;Parra-Fernández, María Del Pilar;Baena-Oliva, Maria Carmen;Valencia-Barrero, Manuel;Potestad, Francisco Eugenio:
FPGA design example for maximum operating frequency measurements. Comunicación en congreso. XIII Technologies Applied to Electronics Teaching Conference (TAEE 2018). Universidad de La Laguna, Canarias. 2018
FPGA design example for maximum operating frequency measurements. Comunicación en congreso. XIII Technologies Applied to Electronics Teaching Conference (TAEE 2018). Universidad de La Laguna, Canarias. 2018
Jimenez-Fernandez, Carlos Jesus;Parra-Fernández, María Del Pilar;Baena-Oliva, Maria Carmen;Valencia-Barrero, Manuel;Potestad, Francisco Eugenio:
Distance measurement as a practical example of FPGA design. Comunicación en congreso. XIII Technologies Applied to Electronics Teaching Conference (TAEE 2018). Universidad de La Laguna, Canarias. 2018
Distance measurement as a practical example of FPGA design. Comunicación en congreso. XIII Technologies Applied to Electronics Teaching Conference (TAEE 2018). Universidad de La Laguna, Canarias. 2018
Potestad, Francisco Eugenio;Jimenez-Fernandez, Carlos Jesus;Valencia-Barrero, Manuel:
Experimental and timing analysis comparison of FPGA Trivium implementations and their vulnerability to clock fault injection. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems (2016). Granada España. 2016
Experimental and timing analysis comparison of FPGA Trivium implementations and their vulnerability to clock fault injection. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems (2016). Granada España. 2016
Potestad, Francisco Eugenio;Jimenez-Fernandez, Carlos Jesus;Valencia-Barrero, Manuel:
Fault Injection on FPGA implementations of Trivium Stream Cipher using Clock Attacks. Poster en Congreso. TRUDEVICE - 6th Conference on Trustworthy Manufacturing and Utilization of Secure Devices. . BARCELONA. 2016
Fault Injection on FPGA implementations of Trivium Stream Cipher using Clock Attacks. Poster en Congreso. TRUDEVICE - 6th Conference on Trustworthy Manufacturing and Utilization of Secure Devices. . BARCELONA. 2016
Jimenez-Fernandez, Carlos Jesus;Potestad, Francisco Eugenio;Valencia-Barrero, Manuel:
Fault Attack on FPGA implementations of Trivium Stream Cipher. Comunicación en congreso. IEEE International Symposium on Circuits and Systems. Montreal, Canada. 2016
Fault Attack on FPGA implementations of Trivium Stream Cipher. Comunicación en congreso. IEEE International Symposium on Circuits and Systems. Montreal, Canada. 2016
Artículos publicados
Potestad, Francisco Eugenio;Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose;Jimenez-Fernandez, Carlos Jesus;Chaves, Ricardo:
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. IEEE Access. 2022. Vol: 10. Pág. 65548-65561. 10.1109/ACCESS.2022.3183764.
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. IEEE Access. 2022. Vol: 10. Pág. 65548-65561. 10.1109/ACCESS.2022.3183764.
Potestad, Francisco Eugenio;Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose;Jimenez-Fernandez, Carlos Jesus;Chaves, Ricardo:
Hardware Countermeasures Benchmarking against Fault Attacks. Applied Sciences. 2022. Vol: 12. Núm: 5. 10.3390/app12052443.
Hardware Countermeasures Benchmarking against Fault Attacks. Applied Sciences. 2022. Vol: 12. Núm: 5. 10.3390/app12052443.
Tena-Sánchez, Erica;Potestad, Francisco Eugenio;Jimenez-Fernandez, Carlos Jesus;Acosta-Jimenez, Antonio Jose;Chaves, Ricardo:
Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks. Applied Sciences. 2022. Vol: 12. Núm: 5. 10.3390/app12052390.
Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks. Applied Sciences. 2022. Vol: 12. Núm: 5. 10.3390/app12052390.
Potestad, Francisco Eugenio;Tena-sanchez, Erica ;Mora-Gutierrez, Jose Miguel;Valencia-Barrero, Manuel;Jimenez-Fernandez, Carlos Jesus:
Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA. IEEE Access. 2021. Vol: 9. Pág. 168444-168454. 10.1109/ACCESS.2021.3136609.
Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA. IEEE Access. 2021. Vol: 9. Pág. 168444-168454. 10.1109/ACCESS.2021.3136609.
Jimenez-Fernandez, Carlos Jesus;Baena-Oliva, Maria Carmen;Parra-Fernández, María Del Pilar;Potestad, Francisco Eugenio;Valencia-Barrero, Manuel:
An Academic Approach to FPGA Design Based on a Distance Meter Circuit. IEEE Journal of Latin-American Learning Technologies. 2020. Vol: 15. Núm: 3. Pág. 123-128. 10.1109/RITA.2020.3008343.
An Academic Approach to FPGA Design Based on a Distance Meter Circuit. IEEE Journal of Latin-American Learning Technologies. 2020. Vol: 15. Núm: 3. Pág. 123-128. 10.1109/RITA.2020.3008343.
Potestad, Francisco Eugenio;Jimenez-Fernandez, Carlos Jesus;Valencia-Barrero, Manuel:
Vulnerability Analysis of Trivium FPGA Implementations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017. Vol: 25. Núm: 12. Pág. 3380-3389. 10.1109/TVLSI.2017.2751151.
Vulnerability Analysis of Trivium FPGA Implementations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017. Vol: 25. Núm: 12. Pág. 3380-3389. 10.1109/TVLSI.2017.2751151.
