Directorio
MARIA JOSE AVEDILLO DE JUAN
Categoría
Catedrático de Universidad
Contacto
Correo electrónico
Departamento
Área
Electrónica
Docencia
Investigación
Grupo de investigación
DISEÑO Y TEST DE CIRCUITOS INTEGRADOS DE SEÑAL MIXTA (DISEÑO Y TEST DE CIRCUITOS INT)
Proyectos y contratos de investigación
DISEÑO E IMPLEMENTACION DE CIRCUITOS MONOLITICOS NANO-MICROELECTRONICOS BASADOS EN EL EFECTO TUNEL RESONANTE (TEC2004-02948 - Investigador/a)
TÉCNICAS DE DISEÑO Y TEST DE CIRCUITOS INTEGRADOS MIXTOS EN TECNOLOGÍAS EMERGENTES (EXC/2005/TIC-927 - Investigador/a)
DISEÑO E IMPLEMENTACIÓN DE CIRCUITOS NANO-MICROELECTRÓNICOS USANDO DISPOSITIVOS CON CARACTERÍSTICAS NDR (TEC2007-67245/MIC - Responsable)
DISEÑO E IMPLEMENTACIÓN DE CIRCUITOS MULTIVALUADOS USANDO DISPOSITIVOS CON CARACTERÍSTICA NDR (P07-TIC-02961 - Investigador/a)
AYUDA A LA CONSOLIDACION DE GRUPOS DE INVESTIGACION - TIC 178 (CONVOCATORIA 2007) (P-2008/560 - Investigador/a)
AYUDA A LA CONSOLIDACION DE GRUPOS DE INVESTIGACION - TIC 178 CONVOCATORIA 2008 (2009/00000431 - Investigador/a)
AYUDA A LA CONSOLIDACION DE GRUPOS DE INVESTIGACIÓN.- TIC 178 CONVOCATORIA 2009 (2009/00001257 - Investigador/a)
FORTALECIMIENTO INSTITUC. DE LAS ACTI. DE POSTGRADO E INVEST. EN SISTEMAS ELECTRÓNICOS INTEGRADOS EN EL INSTITUTO SUPERIOR POLITÉCNICO JOSE A. ECHEVAR (D/024124/09 - Investigador/a)
ARQUITECTURAS Y CIRCUITOS CON RTDS PARA APLICACIONES LÓGICAS Y NO LINEALES (TEC2010/18937 - Responsable)
FORTIN: Fortalecimiento institucional de las actividades de postgrado e investigación en sistemas electrónicos integrados en el Instituto Superior Pol (D030769/10 - Investigador/a)
CIRCUITOS INTEGRADOS DE SEÑAL MIXTA EN TECNOLOGIAS CMOS-SOI (TIC2001-1594 - Investigador/a)
TECNICAS DE DISEÑO E IMPLEMENTACION DE CIRCUITOS AUTOTEMPORIZADOS (TIC95-0094 - Investigador/a)
CIRCUITOS PARA PROCESADO DE SEÑAL CON BAJA TENSION DE ALIMENTACION Y BAJA POTENCIA (TIC97-0648 - Investigador/a)
DISEÑO E IMPLEMENTACION DE UN BIOFONO DIGITAL CMOS DE BAJO CONSUMO-1FD1997-2351 (1FD1997-2351 - Investigador/a)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-036/03 - Investigador/a)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (ESPRIT 21458-SIGYRO) (OG-062/00 - Investigador/a)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (ESPRIT 25213-TARDIS) (OG-063/00 - Investigador/a)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (ESPRIT 26354-ASTERIS) (OG-067/00 - Investigador/a)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-020/02 - Investigador/a)
ARTICULO 11/45 DEL PROYECTO ASTERIS (2000/999 - Investigador/a)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST. (SPRING-IST-1999-12342) (OG-023/02 - Investigador/a)
ARTICULO 68/83 DEL PROYECTO MICROCARD (2003/639 - Investigador/a)
MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (68/83) (OG-080/04 - Investigador/a)
FREQUENCY DISCRIMINATION FILTER FOR ROTATION APPLICATIONS WITH MAGNETIC-SWITCHES: DEMONSTRATOR BOARD AND SYSTEM INTEGRATION (940224 - Investigador/a)
Power, reliability and security challenges in advanced CMOS and beyond-CMOS devices and circuits (RESURGENCE) (US-1380876 - Investigador/a)
Circuitos y Arquitecturas con Dispositivos Steep Slope para Aplicaciones de muy Bajo Consumo de Potencia (TEC2017-87052-P - Responsable)
Nano-Arquitecturas para Computación Lógica Usando Dispositivos Emergentes (TEC2013-40670-P - Responsable)
Capítulos en Libros
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
ANALYTIC APPROACH TO THE OPERATION OF RTD TERNARY INVERTERS BASED ON MML. Pág. 97-112. IN-TECH. IN-TECH. 2010.
ANALYTIC APPROACH TO THE OPERATION OF RTD TERNARY INVERTERS BASED ON MML. Pág. 97-112. IN-TECH. IN-TECH. 2010.
Rodriguez-Villegas, Esther;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Rueda-,A:
THRESHOLD LOGIC BASED ADDERS USING FLOATING-GATE CIRCUITS. Pág. 54-58. DESCONOCIDO. DESCONOCIDO. 2000.
THRESHOLD LOGIC BASED ADDERS USING FLOATING-GATE CIRCUITS. Pág. 54-58. DESCONOCIDO. DESCONOCIDO. 2000.
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
DELAY CIRCUITS. Pág. 127-139. En: 5. DESCONOCIDO. DESCONOCIDO. 1999.
DELAY CIRCUITS. Pág. 127-139. En: 5. DESCONOCIDO. DESCONOCIDO. 1999.
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Rueda-,A:
THRESHOLD LOGIC. Pág. 178-190. En: 22. DESCONOCIDO. DESCONOCIDO. 1999.
THRESHOLD LOGIC. Pág. 178-190. En: 22. DESCONOCIDO. DESCONOCIDO. 1999.
Asistencia a congresos
Jiménez, Manuel;Avedillo-De, Maria Jose;Linares-Barranco, Bernabe;Nuñez-Martínez, Juan:
Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory. Comunicación en congreso. XXXVIII Conference on Design of Circuits and Integrated Systems. Málaga, Spain. 2023
Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory. Comunicación en congreso. XXXVIII Conference on Design of Circuits and Integrated Systems. Málaga, Spain. 2023
Jiménez, Manuel;Nuñez-Martínez, Juan;Shamsi, Jafar;Linares-Barranco, Bernabe;Avedillo-De, Maria Jose:
Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks. Comunicación en congreso. XXXVIII Conference on Design of Circuits and Integrated Systems. Málaga, Spain. 2023
Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks. Comunicación en congreso. XXXVIII Conference on Design of Circuits and Integrated Systems. Málaga, Spain. 2023
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Jiménez, Manuel:
Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. Comunicación en congreso. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Funchal, Madeira, Portugal. 2023
Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. Comunicación en congreso. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Funchal, Madeira, Portugal. 2023
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Jiménez, Manuel:
Solving Combinatorial Optimization Problems with Coupled Phase Transition based Oscillators. Comunicación en congreso. 2022 XXXVII IEEE Conference on Design of Circuits and Integrated Systems (DCIS). Pamplona, Navarra, España. 2022
Solving Combinatorial Optimization Problems with Coupled Phase Transition based Oscillators. Comunicación en congreso. 2022 XXXVII IEEE Conference on Design of Circuits and Integrated Systems (DCIS). Pamplona, Navarra, España. 2022
Jiménez, Manuel;Avedillo-De, Maria Jose;Nuñez-Martínez, Juan;Linares-Barranco, Bernabe:
Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. Comunicación en congreso. 2022 XXXVII IEEE Conference on Design of Circuits and Integrated Systems (DCIS). Pamplona, Navarra, España. 2022
Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. Comunicación en congreso. 2022 XXXVII IEEE Conference on Design of Circuits and Integrated Systems (DCIS). Pamplona, Navarra, España. 2022
Abernot, Madeleine;Jiménez, Manuel;Avedillo-De, Maria Jose:
Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4. Comunicación en congreso. IEEE International Joint Conference on Neural Networks. Padua, Italy. 2022
Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4. Comunicación en congreso. IEEE International Joint Conference on Neural Networks. Padua, Italy. 2022
Nuñez-Martínez, Juan;Jiménez, Manuel;Avedillo-De, Maria Jose:
FeFETs for Phase Encoded Oscillatory based computing. Comunicación en congreso. 2021 XXXVI IEEE Conference on Design of Circuits and Integrated Systems (DCIS),. Vila Do Conde, Oporto, Portugal. 2021
FeFETs for Phase Encoded Oscillatory based computing. Comunicación en congreso. 2021 XXXVI IEEE Conference on Design of Circuits and Integrated Systems (DCIS),. Vila Do Conde, Oporto, Portugal. 2021
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Steep-slope Devices for Power Efficient Adiabatic Logic Circuits. Comunicación en congreso. XXXV Conference on Design of Circuits and Integrated Systems. Segovia. 2020
Steep-slope Devices for Power Efficient Adiabatic Logic Circuits. Comunicación en congreso. XXXV Conference on Design of Circuits and Integrated Systems. Segovia. 2020
Jiménez, Manuel;Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
An Approach to the Device-Circuit Co-Design of HyperFET Circuits. Comunicación en congreso. International Symposium on Circuits and Systems. Sevilla, España. 2020
An Approach to the Device-Circuit Co-Design of HyperFET Circuits. Comunicación en congreso. International Symposium on Circuits and Systems. Sevilla, España. 2020
Nuñez-Martínez, Juan;Jiménez, Manuel;Avedillo-De, Maria Jose:
Device circuit co-design of HyperFET transistors. Comunicación en congreso. 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS). BILBAO (ESPAÑA). 2019
Device circuit co-design of HyperFET transistors. Comunicación en congreso. 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS). BILBAO (ESPAÑA). 2019
Quintero-Alvarez, Héctor Javier;Jiménez, Manuel;Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Inverting versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. Comunicación en congreso. 15TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN. - Praga, República Checa. 2018
Inverting versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. Comunicación en congreso. 15TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN. - Praga, República Checa. 2018
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Exploring Logic Architectures Suitable for TFETs Devices. Comunicación en congreso. 2017 IEEE International Symposium on Circuits and Systems (ISCAS). Baltimore, MD, USA. 2017
Exploring Logic Architectures Suitable for TFETs Devices. Comunicación en congreso. 2017 IEEE International Symposium on Circuits and Systems (ISCAS). Baltimore, MD, USA. 2017
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Complementary Tunnel Gate Topology to Reduce Crosstalk Effects. Comunicación en congreso. XXXI CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS DCIS 2016. GRANADA. 2016
Complementary Tunnel Gate Topology to Reduce Crosstalk Effects. Comunicación en congreso. XXXI CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS DCIS 2016. GRANADA. 2016
Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits. Comunicación en congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). BREMEN, ALEMANIA. 2016
Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits. Comunicación en congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). BREMEN, ALEMANIA. 2016
Calahorro, Jose Manuel ;Acasandrei-, Laurentiu;Barriga-Barros, Angel;Avedillo-De, Maria Jose:
Experiencia en desarrollo de sistemas empotrados hardware-software como Trabajo Fin de Grado. Comunicación en congreso. XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica. Sevilla (España). 2016
Experiencia en desarrollo de sistemas empotrados hardware-software como Trabajo Fin de Grado. Comunicación en congreso. XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica. Sevilla (España). 2016
Avedillo-De, Maria Jose;Barriga-Barros, Angel;Acasandrei-, Laurentiu;Calahorro, Jose Manuel:
Hardware-Software Embedded Face Recognition System. Poster en Congreso. 24th International Conference in Central Europe on Computer Graphics, Visualization and Computer Vision . Plzen, Czech Republic. 2016
Hardware-Software Embedded Face Recognition System. Poster en Congreso. 24th International Conference in Central Europe on Computer Graphics, Visualization and Computer Vision . Plzen, Czech Republic. 2016
Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Assessing application areas for tunnel transistor technologies. Comunicación en congreso. Design of Integrated Circuits and Systems 2015. Lisboa. 2015
Assessing application areas for tunnel transistor technologies. Comunicación en congreso. Design of Integrated Circuits and Systems 2015. Lisboa. 2015
Quintero-Alvarez, Héctor Javier;Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Improving robustness of dynamic logic based pipelines. Comunicación en congreso. Design of Circuits and Integrated Systems 2015. . 2015
Improving robustness of dynamic logic based pipelines. Comunicación en congreso. Design of Circuits and Integrated Systems 2015. . 2015
Nuñez-Martínez, Juan;Quintero-Alvarez, Héctor Javier;Avedillo-De, Maria Jose:
DOE based high-performance gate-level pipelines. Comunicación en congreso. Powe and Timming Modeling, Optimization and Simulation International Workshop. Palma de Mallorca. 2014
DOE based high-performance gate-level pipelines. Comunicación en congreso. Powe and Timming Modeling, Optimization and Simulation International Workshop. Palma de Mallorca. 2014
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Quintero-Alvarez, Héctor Javier:
Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. . 2013
Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. . 2013
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Novel dynamic gate topology for superpipelines in DSM technologies. Comunicación en congreso. Digital System Design EUROMICRO. Santander. 2013
Novel dynamic gate topology for superpipelines in DSM technologies. Comunicación en congreso. Digital System Design EUROMICRO. Santander. 2013
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IEEE International Conference on Electronics, Circuits, and Systems . SEVILLA, ESPAÑA. 2012
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IEEE International Conference on Electronics, Circuits, and Systems . SEVILLA, ESPAÑA. 2012
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications. Comunicación en congreso. International Workshop on Power and Timing Modeling, Optimization and Simulation . NEWCASTLE, REINO UNIDO, United Kingdom. 2012
Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications. Comunicación en congreso. International Workshop on Power and Timing Modeling, Optimization and Simulation . NEWCASTLE, REINO UNIDO, United Kingdom. 2012
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Compact and Power Efficient MOS-NDR Muller C-Elements. Comunicación en congreso. Doctoral Conference on Computing, Electrical and Industrial Systems. CAPARICA (LISBOA). 2012
Compact and Power Efficient MOS-NDR Muller C-Elements. Comunicación en congreso. Doctoral Conference on Computing, Electrical and Industrial Systems. CAPARICA (LISBOA). 2012
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IBERCHIP 2012. PLAYA DEL CARMEN, MEXICO. 2012
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IBERCHIP 2012. PLAYA DEL CARMEN, MEXICO. 2012
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Efficient Realization of RTD-CMOS Logic Gates. Comunicación en congreso. Great Lakes Symposium on VLSI. LAUSSANE, SUIZA. 2011
Efficient Realization of RTD-CMOS Logic Gates. Comunicación en congreso. Great Lakes Symposium on VLSI. LAUSSANE, SUIZA. 2011
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs. Comunicación en congreso. SPIE 2011. PRAGA, REPÚBLICA CHECA. 2011
Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs. Comunicación en congreso. SPIE 2011. PRAGA, REPÚBLICA CHECA. 2011
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
EVALUATION OF RTD-CMOS LOGIC GATES. Comunicación en congreso. DSD EUROMICRO 2010 () (.2010.LILLE, FRANCIA). LILLE, FRANCIA. 2010
EVALUATION OF RTD-CMOS LOGIC GATES. Comunicación en congreso. DSD EUROMICRO 2010 () (.2010.LILLE, FRANCIA). LILLE, FRANCIA. 2010
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
SINGLE PHASE MOS-NDR MOBILE NETWORKS. Comunicación en congreso. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1979-1982, Jun. 2010. PARIS, FRANCE. 2010
SINGLE PHASE MOS-NDR MOBILE NETWORKS. Comunicación en congreso. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1979-1982, Jun. 2010. PARIS, FRANCE. 2010
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
REDES MOBILE MOS-NDR OPERANDO CON RELOJ DE UNA FASE. Comunicación en congreso. IBERCHIP 2010 () (.2010.IGUAZÚ (BRASIL)). IGUAZÚ (BRASIL). 2010
REDES MOBILE MOS-NDR OPERANDO CON RELOJ DE UNA FASE. Comunicación en congreso. IBERCHIP 2010 () (.2010.IGUAZÚ (BRASIL)). IGUAZÚ (BRASIL). 2010
Pettenghi-Roldan, Hector;Chaves-,Ricardo;Sousa-,Lionel;Avedillo-De, Maria Jose:
AN IMPROVED RNS GENERATOR 2N ± K BASED ON THRESHOLD LOGIC. Comunicación en congreso. IEEE/IFIP VLSI-SOC () (.2010.MADRID). . 2010
AN IMPROVED RNS GENERATOR 2N ± K BASED ON THRESHOLD LOGIC. Comunicación en congreso. IEEE/IFIP VLSI-SOC () (.2010.MADRID). . 2010
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
DC OPERATION LIMITS FOR MOBILE INVERTERS. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (24) (24.2009.Zaragoza). Zaragoza. 2009
DC OPERATION LIMITS FOR MOBILE INVERTERS. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (24) (24.2009.Zaragoza). Zaragoza. 2009
Bol-, D;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Legat-, J.D.:
MOBILE DIGITAL CIRCUITS BASED ON NEGATIVE-DIFFERENTIAL-RESISTANCE MOS STRUCTURES. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (24) (24.2009.Zaragoza). Zaragoza. 2009
MOBILE DIGITAL CIRCUITS BASED ON NEGATIVE-DIFFERENTIAL-RESISTANCE MOS STRUCTURES. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (24) (24.2009.Zaragoza). Zaragoza. 2009
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
SINGLE PHASE CLOCK SCHEME FOR MOBILE BASED CIRCUITS. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (24) (24.2009.Zaragoza). Zaragoza. 2009
SINGLE PHASE CLOCK SCHEME FOR MOBILE BASED CIRCUITS. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (24) (24.2009.Zaragoza). Zaragoza. 2009
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Pettenghi-Roldan, Hector;Nuñez-Martínez, Juan:
PUERTAS UMBRAL GENERALIZADAS PARA EL DISEÑO LÓGICOS DE CIRCUITOS MOBILE. Comunicación en congreso. IBERCHIP () (.2009.BUENOS AIRES, ARGENTINA). BUENOS AIRES, ARGENTINA. 2009
PUERTAS UMBRAL GENERALIZADAS PARA EL DISEÑO LÓGICOS DE CIRCUITOS MOBILE. Comunicación en congreso. IBERCHIP () (.2009.BUENOS AIRES, ARGENTINA). BUENOS AIRES, ARGENTINA. 2009
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
MULLER C-ELEMENTS MULTIENTRADA BASADOS EN MOS-NDR. Comunicación en congreso. IBERCHIP () (.2009.BUENOS AIRES, ARGENTINA). BUENOS AIRES, ARGENTINA. 2009
MULLER C-ELEMENTS MULTIENTRADA BASADOS EN MOS-NDR. Comunicación en congreso. IBERCHIP () (.2009.BUENOS AIRES, ARGENTINA). BUENOS AIRES, ARGENTINA. 2009
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
FAST AND AREA EFFICIENT MULTI-INPUT MULLER C-ELEMENT BASED ON MOS-NDR. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS () (.2009.TAIPEI, TAIWAN). TAIPEI, TAIWAN. 2009
FAST AND AREA EFFICIENT MULTI-INPUT MULLER C-ELEMENT BASED ON MOS-NDR. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS () (.2009.TAIPEI, TAIWAN). TAIPEI, TAIWAN. 2009
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
LIMITS TO A CORRECT OPERATION IN RTD-BASED TERNARY INVERTERS. Comunicación en congreso. ISCAS 2008 () (.2008.SEATTLE, WASHINGTON, USA). SEATTLE, WASHINGTON, USA. 2008
LIMITS TO A CORRECT OPERATION IN RTD-BASED TERNARY INVERTERS. Comunicación en congreso. ISCAS 2008 () (.2008.SEATTLE, WASHINGTON, USA). SEATTLE, WASHINGTON, USA. 2008
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
DESIGN OF RTD-BASED NMIN/NMAX GATES. Comunicación en congreso. IEEE NANO 2008 () (.2008.ARLINGTONG, TX, USA). ARLINGTONG, TX, USA. 2008
DESIGN OF RTD-BASED NMIN/NMAX GATES. Comunicación en congreso. IEEE NANO 2008 () (.2008.ARLINGTONG, TX, USA). ARLINGTONG, TX, USA. 2008
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
TRANSIENT RESPONSE IN MOBILE-BASED CIRCUITS. Comunicación en congreso. VLSI-SOC () (.2008.RHODES ISLAND, GREECE). RHODES ISLAND, GREECE. 2008
TRANSIENT RESPONSE IN MOBILE-BASED CIRCUITS. Comunicación en congreso. VLSI-SOC () (.2008.RHODES ISLAND, GREECE). RHODES ISLAND, GREECE. 2008
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
RTD BASED LOGIC CIRCUITS USING GENERALIZED THRESHOLD. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (23) (23.2008.GRENOBLE (FRANCIA)). GRENOBLE (FRANCIA). 2008
RTD BASED LOGIC CIRCUITS USING GENERALIZED THRESHOLD. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (23) (23.2008.GRENOBLE (FRANCIA)). GRENOBLE (FRANCIA). 2008
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
A QUASI DIFFERENTIAL QUANTIZER BASED ON SMOBILE. Comunicación en congreso. IEEE SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (20) (20.2007.RÍO DE JANEIRO (BRAZIL)). RÍO DE JANEIRO (BRAZIL). 2008
A QUASI DIFFERENTIAL QUANTIZER BASED ON SMOBILE. Comunicación en congreso. IEEE SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (20) (20.2007.RÍO DE JANEIRO (BRAZIL)). RÍO DE JANEIRO (BRAZIL). 2008
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
A NOVEL CONTRIBUTION TO THE RTD-BASED THRESHOLD LOGIC FAMILY. Poster en Congreso. ISCAS 2008 () (.2008.SEATTLE, WASHINGTON, USA). SEATTLE, WASHINGTON, USA. 2008
A NOVEL CONTRIBUTION TO THE RTD-BASED THRESHOLD LOGIC FAMILY. Poster en Congreso. ISCAS 2008 () (.2008.SEATTLE, WASHINGTON, USA). SEATTLE, WASHINGTON, USA. 2008
Romeira-,Bruno;Figueiredo-,Jose Maria;Slight-,T.J:;Wang-,L.M.;Wasige-,E.;Ironside-,C.N.;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
OBSERVATION OF FREQUENCY DIVISION AND CHAOS BEHAVIOR IN A LASER DIODE DRIVEN BY A RESONANT TUNNELING DIODE. Comunicación en congreso. CLEO/QELS 2008 () (.2008.DD). DD. 2008
OBSERVATION OF FREQUENCY DIVISION AND CHAOS BEHAVIOR IN A LASER DIODE DRIVEN BY A RESONANT TUNNELING DIODE. Comunicación en congreso. CLEO/QELS 2008 () (.2008.DD). DD. 2008
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
ANALYSIS OF THE CRITICAL RISE TIME IN MOBILE-BASED CIRCUITS. Poster en Congreso. IEEE ICECS () (.2008.MALTA). MALTA. 2008
ANALYSIS OF THE CRITICAL RISE TIME IN MOBILE-BASED CIRCUITS. Poster en Congreso. IEEE ICECS () (.2008.MALTA). MALTA. 2008
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
HOLDING PRESERVING IN RTD-BASED MULTIPLE-VALUED QUANTIZIERS. Comunicación en congreso. IEEE CONFERENCE ON NANOTECHNOLOGY (7) (7.2007.HONG-KONG (CHINA)). HONG-KONG (CHINA). 2007
HOLDING PRESERVING IN RTD-BASED MULTIPLE-VALUED QUANTIZIERS. Comunicación en congreso. IEEE CONFERENCE ON NANOTECHNOLOGY (7) (7.2007.HONG-KONG (CHINA)). HONG-KONG (CHINA). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
ANALYTIC APPROACH TO THE OPERATION OF RTD TERNARY INVERTERS BASED ON MML. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POST-BINARY ULSI SYSTEMS (16) (16.2007.OSLO (NORWAY)). OSLO (NORWAY). 2007
ANALYTIC APPROACH TO THE OPERATION OF RTD TERNARY INVERTERS BASED ON MML. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POST-BINARY ULSI SYSTEMS (16) (16.2007.OSLO (NORWAY)). OSLO (NORWAY). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
LIMITS TO A CORRECT EVALUATION IN RTD-BASED QUATERNARY INVERTERS. Comunicación en congreso. INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (37) (37.2007.OSLO (NORWAY)). OSLO (NORWAY). 2007
LIMITS TO A CORRECT EVALUATION IN RTD-BASED QUATERNARY INVERTERS. Comunicación en congreso. INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (37) (37.2007.OSLO (NORWAY)). OSLO (NORWAY). 2007
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
NON RETURN MOBILE LOGIC FAMILY. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEM (40) (40.2007.NEW ORLEANS, LUSIANA, USA). NEW ORLEANS, LUSIANA, USA. 2007
NON RETURN MOBILE LOGIC FAMILY. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEM (40) (40.2007.NEW ORLEANS, LUSIANA, USA). NEW ORLEANS, LUSIANA, USA. 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
DC OPERATION LIMITS OF RTD TERNARY INVERTERS BASED ON NML. Comunicación en congreso. DCIS () (.2007.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2007
DC OPERATION LIMITS OF RTD TERNARY INVERTERS BASED ON NML. Comunicación en congreso. DCIS () (.2007.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
OPERATION LIMITS IN RTD-BASED TERNARY QUANTIZERS. Comunicación en congreso. ACM GREAT LAKES SYMPOSIUM ON VLSI (17) (17.2007.STRESSA-LAGO MAGGIORE (ITALY)). STRESSA-LAGO MAGGIORE (ITALY). 2007
OPERATION LIMITS IN RTD-BASED TERNARY QUANTIZERS. Comunicación en congreso. ACM GREAT LAKES SYMPOSIUM ON VLSI (17) (17.2007.STRESSA-LAGO MAGGIORE (ITALY)). STRESSA-LAGO MAGGIORE (ITALY). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
CORRECT OPERATION IN SMOBILE-BASED QUASI-DIFFERENTIAL QUANTIZIERS. Comunicación en congreso. ECCTD 2007 () (.2007.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2007
CORRECT OPERATION IN SMOBILE-BASED QUASI-DIFFERENTIAL QUANTIZIERS. Comunicación en congreso. ECCTD 2007 () (.2007.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
CORRECT DC OPERATION IN RTD BASED TERNARY INVERTERS. Comunicación en congreso. IEEE INTERNATIONAL CONFERENCE OF NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS (2) (2.2007.BANGKOK (THAILANDIA)). BANGKOK (THAILANDIA). 2007
CORRECT DC OPERATION IN RTD BASED TERNARY INVERTERS. Comunicación en congreso. IEEE INTERNATIONAL CONFERENCE OF NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS (2) (2.2007.BANGKOK (THAILANDIA)). BANGKOK (THAILANDIA). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
HOLDING DISSAPEARANCE IN RTD-BASED QUANTIZERS. Comunicación en congreso. ENS 2006 () (.2006.PARIS). PARIS. 2006
HOLDING DISSAPEARANCE IN RTD-BASED QUANTIZERS. Comunicación en congreso. ENS 2006 () (.2006.PARIS). PARIS. 2006
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Pettenghi-Roldan, Hector:
IMPLEMENTACIÓN DE LÓGICA UMBRAL Y MULTIUMBRAL CON RTDS. Comunicación en congreso. IBERCHIP (12) (12.2006.SAN JOSE, COSTA RICA). SAN JOSE, COSTA RICA. 2006
IMPLEMENTACIÓN DE LÓGICA UMBRAL Y MULTIUMBRAL CON RTDS. Comunicación en congreso. IBERCHIP (12) (12.2006.SAN JOSE, COSTA RICA). SAN JOSE, COSTA RICA. 2006
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
DC CORRECT OPERATION IN MOBILE INVERTERS. Comunicación en congreso. MWCAS 2006 (49) (49.2006.SAN JUAN (PUERTO RICO)). SAN JUAN (PUERTO RICO). 2006
DC CORRECT OPERATION IN MOBILE INVERTERS. Comunicación en congreso. MWCAS 2006 (49) (49.2006.SAN JUAN (PUERTO RICO)). SAN JUAN (PUERTO RICO). 2006
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Pettenghi-Roldan, Hector:
SELF-LATCHING OPERATION LIMITS FOR MOBILE CIRCUITS. Comunicación en congreso. ISCAS 2006 () (.2006.KOS, GRECIA). KOS, GRECIA. 2006
SELF-LATCHING OPERATION LIMITS FOR MOBILE CIRCUITS. Comunicación en congreso. ISCAS 2006 () (.2006.KOS, GRECIA). KOS, GRECIA. 2006
Bol-, D;Legat-, J.D.;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
MONOSTABLE-BISTABLE TRANSITION LOGIC ELEMENTS: THRESHOLD LOGIC VS. BOOLEAN LOGIC COMPARISON. Comunicación en congreso. ICECS () (.2006.NICE (FRANCE)). NICE (FRANCE). 2006
MONOSTABLE-BISTABLE TRANSITION LOGIC ELEMENTS: THRESHOLD LOGIC VS. BOOLEAN LOGIC COMPARISON. Comunicación en congreso. ICECS () (.2006.NICE (FRANCE)). NICE (FRANCE). 2006
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
OPERATION LIMITS FOR MOBILE FOLLOWERS. Comunicación en congreso. NANO 2006 (6) (6.2006.CINCINNATI). CINCINNATI. 2006
OPERATION LIMITS FOR MOBILE FOLLOWERS. Comunicación en congreso. NANO 2006 (6) (6.2006.CINCINNATI). CINCINNATI. 2006
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
LIMITS TO A CORRECT EVALUATION IN RTD BASED TERNARY INVERTERS. Comunicación en congreso. ICECS () (.2006.NICE (FRANCE)). NICE (FRANCE). 2006
LIMITS TO A CORRECT EVALUATION IN RTD BASED TERNARY INVERTERS. Comunicación en congreso. ICECS () (.2006.NICE (FRANCE)). NICE (FRANCE). 2006
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
OPERATION LIMITS FOR MOBILE FOLLOWER. Comunicación en congreso. NANO 2006 (6) (6.2006.CINCINNATI). CINCINNATI. 2006
OPERATION LIMITS FOR MOBILE FOLLOWER. Comunicación en congreso. NANO 2006 (6) (6.2006.CINCINNATI). CINCINNATI. 2006
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
DESIGN GUIDES FOR A CORRECT DC OPERATION IN RTD-BASED THRESHOLD GATES. Comunicación en congreso. IEEE EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN () (.2006.CAVTAT, CROACIA). CAVTAT, CROACIA. 2006
DESIGN GUIDES FOR A CORRECT DC OPERATION IN RTD-BASED THRESHOLD GATES. Comunicación en congreso. IEEE EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN () (.2006.CAVTAT, CROACIA). CAVTAT, CROACIA. 2006
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Huertas-Diaz, Jose Luis:
ROBUST FREQUENCY DIVIDER BASED ON RESONANT TUNNELING DEVICES. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS: ISCAS 2005 (.2005.KOBE, JAPÓN). KOBE, JAPÓN. 2005
ROBUST FREQUENCY DIVIDER BASED ON RESONANT TUNNELING DEVICES. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS: ISCAS 2005 (.2005.KOBE, JAPÓN). KOBE, JAPÓN. 2005
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Pettenghi-Roldan, Hector:
LOGIC MODELS SUPPORTING THE DESIGN OF MOBILE-BASED RTD CIRCUITS. Comunicación en congreso. IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURE PROCESSORS (16.2005.SAMOS, GRECIA). SAMOS, GRECIA. 2005
LOGIC MODELS SUPPORTING THE DESIGN OF MOBILE-BASED RTD CIRCUITS. Comunicación en congreso. IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURE PROCESSORS (16.2005.SAMOS, GRECIA). SAMOS, GRECIA. 2005
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
NEW CIRCUIT TOPOLOGY FOR LOGIC GATES BASED ON RTD'S. Comunicación en congreso. IEEE CONFERENCE ON NANOTECHNOLOGY (5) (5.2005.NAGOYA, JAPÓN). NAGOYA, JAPÓN. 2005
NEW CIRCUIT TOPOLOGY FOR LOGIC GATES BASED ON RTD'S. Comunicación en congreso. IEEE CONFERENCE ON NANOTECHNOLOGY (5) (5.2005.NAGOYA, JAPÓN). NAGOYA, JAPÓN. 2005
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
NANOPIPELINED RTD ADDERS USING MULTI-THRESHOLD THRESHOLD GATES. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS DCIS 2005 (20.2005.LISBOA). LISBOA. 2005
NANOPIPELINED RTD ADDERS USING MULTI-THRESHOLD THRESHOLD GATES. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS DCIS 2005 (20.2005.LISBOA). LISBOA. 2005
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
USING MULTI-THRESHOLD GATES IN RTD-BASED LOGIC DESIGN. Comunicación en congreso. EUROPEAN NANO SYSTMES CONFERENCE (ENS 2005) () (.2005.PARÍS, FRANCIA). PARÍS, FRANCIA. 2005
USING MULTI-THRESHOLD GATES IN RTD-BASED LOGIC DESIGN. Comunicación en congreso. EUROPEAN NANO SYSTMES CONFERENCE (ENS 2005) () (.2005.PARÍS, FRANCIA). PARÍS, FRANCIA. 2005
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
A THRESHOLD LOGIC SYNTHESIS TOOL FOR RTD CIRCUITS. Comunicación en congreso. EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN (DSD'04) () (.2004.RENNES, FRANCIA). RENNES, FRANCIA. 2004
A THRESHOLD LOGIC SYNTHESIS TOOL FOR RTD CIRCUITS. Comunicación en congreso. EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN (DSD'04) () (.2004.RENNES, FRANCIA). RENNES, FRANCIA. 2004
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
USEFUL LOGIC BLOCKS ON CLOCKED SERIES-CONNECTED RTDS. Comunicación en congreso. 4TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE_NANO 2004) (4) (4.2004.MUNICH, ALEMANIA). MUNICH, ALEMANIA. 2004
USEFUL LOGIC BLOCKS ON CLOCKED SERIES-CONNECTED RTDS. Comunicación en congreso. 4TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE_NANO 2004) (4) (4.2004.MUNICH, ALEMANIA). MUNICH, ALEMANIA. 2004
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Pettenghi-Roldan, Hector:
PROGRAMMABLE LOGIC GATE BASED ON RESONANT TUNNELING DEVICES. Comunicación en congreso. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS () (.2004.VANCOUVER, CANADA). VANCOUVER, CANADA. 2004
PROGRAMMABLE LOGIC GATE BASED ON RESONANT TUNNELING DEVICES. Comunicación en congreso. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS () (.2004.VANCOUVER, CANADA). VANCOUVER, CANADA. 2004
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Pettenghi-Roldan, Hector:
RTD-BASED COMPACT PROGRAMMABLE GATES. Comunicación en congreso. INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN 2004) () (.2004.BUDAPEST, HUNGRÍA). BUDAPEST, HUNGRÍA. 2004
RTD-BASED COMPACT PROGRAMMABLE GATES. Comunicación en congreso. INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN 2004) () (.2004.BUDAPEST, HUNGRÍA). BUDAPEST, HUNGRÍA. 2004
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
A CAD TOOL FOR THE DESIGN OF RTD PROGRAMMABLE GATES BASED ON MOBILE. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (19.2004.BORDEAUX, FRANCIA). BORDEAUX, FRANCIA. 2004
A CAD TOOL FOR THE DESIGN OF RTD PROGRAMMABLE GATES BASED ON MOBILE. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (19.2004.BORDEAUX, FRANCIA). BORDEAUX, FRANCIA. 2004
Vazquez-Garcia De La Vega, Diego;Huertas-Sánchez, Gloria;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Rueda-Rueda, Adoracion;Huertas-Diaz, Jose Luis:
A LP-LV HIGH PERFORMANCE MONOLITIC DTMF RECEIVER WITH ON-CHIP TEST FACILITIES. Comunicación en congreso. SPIE'S INTERNATIONAL SYMPOSIUM ON MICROTECHNOLOGIES FOR THE NEW MILLENIUM (SPIE'03) () (.2003.MAS PALOMAS, GRAN CANARIA, ESPAÑA). MAS PALOMAS, GRAN CANARIA, ESPAÑA. 2003
A LP-LV HIGH PERFORMANCE MONOLITIC DTMF RECEIVER WITH ON-CHIP TEST FACILITIES. Comunicación en congreso. SPIE'S INTERNATIONAL SYMPOSIUM ON MICROTECHNOLOGIES FOR THE NEW MILLENIUM (SPIE'03) () (.2003.MAS PALOMAS, GRAN CANARIA, ESPAÑA). MAS PALOMAS, GRAN CANARIA, ESPAÑA. 2003
Beiu-,V;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
REVIEW OF DIFFERENTIAL THRESHOLD GATE IMPLEMENTATIONS. Comunicación en congreso. IASTED INTERNATIONAL CONFERENCE ON NEURAL NETWORKS AND COMPUTATIONAL INTELLIEGENCE (NCI 2003) () (.2003.TIJUANA, MÉJICO). TIJUANA, MÉJICO. 2003
REVIEW OF DIFFERENTIAL THRESHOLD GATE IMPLEMENTATIONS. Comunicación en congreso. IASTED INTERNATIONAL CONFERENCE ON NEURAL NETWORKS AND COMPUTATIONAL INTELLIEGENCE (NCI 2003) () (.2003.TIJUANA, MÉJICO). TIJUANA, MÉJICO. 2003
Beiu-,V;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
REVIEW OF CAPACITIVE THRESHOLD GATE IMPLEMENTATIONS. Comunicación en congreso. INTERNATIONAL CONFERENCE ON ARTIFICIAL NEURAL NETWORKS (ICANN 2003) () (.2003.ESTAMBUL, TURQUÍA). ESTAMBUL, TURQUÍA. 2003
REVIEW OF CAPACITIVE THRESHOLD GATE IMPLEMENTATIONS. Comunicación en congreso. INTERNATIONAL CONFERENCE ON ARTIFICIAL NEURAL NETWORKS (ICANN 2003) () (.2003.ESTAMBUL, TURQUÍA). ESTAMBUL, TURQUÍA. 2003
Beiu-,V;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Andonie-,R:
DIFFERENTIAL IMPLEMENTATIONS OF THRESHOLD LOGIC GATES. Comunicación en congreso. INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS (SCS 2003) () (.2003.IASI, RUMANÍA). IASI, RUMANÍA. 2003
DIFFERENTIAL IMPLEMENTATIONS OF THRESHOLD LOGIC GATES. Comunicación en congreso. INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS (SCS 2003) () (.2003.IASI, RUMANÍA). IASI, RUMANÍA. 2003
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Pettenghi-Roldan, Hector;El-Alami-,H:
DESIGN OF RESIDUE GENERATORS MODULO-3 USING THRESHOLD LOGIC. Comunicación en congreso. CONFERENCIA DE DISEÑO DE CIRCUITOS INTEGRADOS Y SISTEMAS (18.2003.CIUDAD REAL ). CIUDAD REAL. 2003
DESIGN OF RESIDUE GENERATORS MODULO-3 USING THRESHOLD LOGIC. Comunicación en congreso. CONFERENCIA DE DISEÑO DE CIRCUITOS INTEGRADOS Y SISTEMAS (18.2003.CIUDAD REAL ). CIUDAD REAL. 2003
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
BEYOND THRESHOLD LOGIC: MULTI-THRESHOLD THRESHOLD LOGIC. Comunicación en congreso. MEL-ARI-NID WORKSHOP (.2003.TOULOUSE, FRANCIA). TOULOUSE, FRANCIA. 2003
BEYOND THRESHOLD LOGIC: MULTI-THRESHOLD THRESHOLD LOGIC. Comunicación en congreso. MEL-ARI-NID WORKSHOP (.2003.TOULOUSE, FRANCIA). TOULOUSE, FRANCIA. 2003
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Rodriguez-Villegas, Esther;Rueda-,A:
THRESHOLD-LOGIC-BASED DESIGN OF COMPRESSORS. Comunicación en congreso. INTERNATIONAL CONFERENCE ON ELECTRONIC CIRCUITS AND SYSTEMS (.2002.DUBROVNIK, CROACIA). DUBROVNIK, CROACIA. 2002
THRESHOLD-LOGIC-BASED DESIGN OF COMPRESSORS. Comunicación en congreso. INTERNATIONAL CONFERENCE ON ELECTRONIC CIRCUITS AND SYSTEMS (.2002.DUBROVNIK, CROACIA). DUBROVNIK, CROACIA. 2002
Avedillo-De, Maria Jose;Rueda-,A:
SIMPLE PARALLEL WEIGHTED ORDER STATISTIC FILTER IMPLEMENTATIONS. Conferencia Congreso no publicada. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (.2002.-). -. 2002
SIMPLE PARALLEL WEIGHTED ORDER STATISTIC FILTER IMPLEMENTATIONS. Conferencia Congreso no publicada. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (.2002.-). -. 2002
Martínez-Pérez, Manuel;Rodriguez-Villegas, Esther;Serrano-Gotarredona, Maria Teresa;Baeza-Alvarez, Juan Manuel;Rueda-Rueda, Adoracion;Perez-Cabello, Maria Teresa;Repiso-Asuero, Juan Manuel;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Huertas-Sánchez, Gloria;Yufera-Garcia, Alberto;Linares-Barranco, Bernabe;Muñoz-Hinojosa, José María;Arias-Drake, Alberto;Guerra-Gutiérrez, Pedro;Doldan-Lorenzo, Ricardo;El-Gmili, Hakim;Leger-, Gildas:
A VHDL BEHAVIOURAL MODEL FOR PIPELINE ADCS. Comunicación en congreso. NUEVAS PERSPECTIVAS EN LA INTERVENCION PSICOPEDAGOGICA: II. ORIENTACION, EDUCAION ESPECIAL Y FORMACION DEL PROFESORADO (.2002.MADRID, ESPAÑA). . 2002
A VHDL BEHAVIOURAL MODEL FOR PIPELINE ADCS. Comunicación en congreso. NUEVAS PERSPECTIVAS EN LA INTERVENCION PSICOPEDAGOGICA: II. ORIENTACION, EDUCAION ESPECIAL Y FORMACION DEL PROFESORADO (.2002.MADRID, ESPAÑA). . 2002
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Huertas-Diaz, Jose Luis:
SIMPLIFIED REED-MULLER EXPRESSIONS FOR RESIDUE THRESHOLD FUNCTIONS. Conferencia Congreso no publicada. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (.2002.-). -. 2002
SIMPLIFIED REED-MULLER EXPRESSIONS FOR RESIDUE THRESHOLD FUNCTIONS. Conferencia Congreso no publicada. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (.2002.-). -. 2002
Martínez-Pérez, Manuel;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Koegst-,M;Ruelke-,S;Susse-,H:
AN ENCODING TECHNIQUE FOR LOW POWER CMOS IMPLEMENTATIONS OF CONTROLLERS. Comunicación en congreso. DESIGN, AUTOMATION TEST IN EUROPE (.2002.PARIS). PARIS. 2002
AN ENCODING TECHNIQUE FOR LOW POWER CMOS IMPLEMENTATIONS OF CONTROLLERS. Comunicación en congreso. DESIGN, AUTOMATION TEST IN EUROPE (.2002.PARIS). PARIS. 2002
Rodriguez-Villegas, Esther;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Rueda-,A:
HIGH-SPEED LOW-POWER LOGIC GATES USING FLOATING GATES. Conferencia Congreso no publicada. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (.2002.-). -. 2002
HIGH-SPEED LOW-POWER LOGIC GATES USING FLOATING GATES. Conferencia Congreso no publicada. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (.2002.-). -. 2002
Martínez-Pérez, Manuel;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Huertas-Diaz, Jose Luis:
A FLEXIBLE STATE ASSIGNMENT ALGORITHM FOR LOW POWER IMPLEMENTATIONS. Comunicación en congreso. PROC. DESIGN CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (15.2001.OPORTO). OPORTO. 2001
A FLEXIBLE STATE ASSIGNMENT ALGORITHM FOR LOW POWER IMPLEMENTATIONS. Comunicación en congreso. PROC. DESIGN CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE (15.2001.OPORTO). OPORTO. 2001
Vazquez-Garcia De La Vega, Diego;Avedillo-De, Maria Jose;Huertas-Sánchez, Gloria;Quintana-Toledo, Jose Maria;Pauristsch-,M;Rueda-Rueda, Adoracion;Huertas-Diaz, Jose Luis:
A LOW-VOLTAGE LOW-POWER HIGH PERFORMANCE FULLY INTEGRATED DTMF RECEIVER. Comunicación en congreso. EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (27.2001.VILLACH, AUSTRIA). VILLACH, AUSTRIA. 2001
A LOW-VOLTAGE LOW-POWER HIGH PERFORMANCE FULLY INTEGRATED DTMF RECEIVER. Comunicación en congreso. EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (27.2001.VILLACH, AUSTRIA). VILLACH, AUSTRIA. 2001
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Rodriguez-Villegas, Esther:
IMPROVED COMPRESSOR DESIGNS BASES ON THRESHOLD LOGIC. Comunicación en congreso. SEMINARIO ANUAL DE AUTOMÁTICA, ELECTRÓNICA INDUSTRIAL E INSTRUMENTACIÓN. SAAEI 2001 (.2001.MATANZAS, CUBA). MATANZAS, CUBA. 2001
IMPROVED COMPRESSOR DESIGNS BASES ON THRESHOLD LOGIC. Comunicación en congreso. SEMINARIO ANUAL DE AUTOMÁTICA, ELECTRÓNICA INDUSTRIAL E INSTRUMENTACIÓN. SAAEI 2001 (.2001.MATANZAS, CUBA). MATANZAS, CUBA. 2001
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Jiménez-Naharro, Raúl;Rodriguez-Villegas, Esther:
LOW-POWER LOGIC STYLES FOR FULL-ADDER CIRCUITS. Comunicación en congreso. INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (8.2001.MALTA). MALTA. 2001
LOW-POWER LOGIC STYLES FOR FULL-ADDER CIRCUITS. Comunicación en congreso. INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (8.2001.MALTA). MALTA. 2001
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Jiménez-Naharro, Raúl:
PASS TRANSISTOR THRESHOLD GATES. APPLICATIONS TO WOS FILTERS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON LOGIC & SYNTHESIS (10.2001.GRANLIBAKKEN, CALIFORNIA). GRANLIBAKKEN, CALIFORNIA. 2001
PASS TRANSISTOR THRESHOLD GATES. APPLICATIONS TO WOS FILTERS. Comunicación en congreso. INTERNATIONAL WORKSHOP ON LOGIC & SYNTHESIS (10.2001.GRANLIBAKKEN, CALIFORNIA). GRANLIBAKKEN, CALIFORNIA. 2001
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
REED-MULLER DESCRIPTION OF SYMMETRIC FUNCTIONS. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (33.2001.SYDNEY). SYDNEY. 2001
REED-MULLER DESCRIPTION OF SYMMETRIC FUNCTIONS. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (33.2001.SYDNEY). SYDNEY. 2001
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Jiménez-Naharro, Raúl;Rodriguez-Villegas, Esther:
PRACTICAL LOW-COST CPL IMPLEMENATIONS OF THRESHOLD LOGIC FUNCTIONS. Comunicación en congreso. GLSVLSI (1.2001.DESCONOCIDO). DESCONOCIDO. 2001
PRACTICAL LOW-COST CPL IMPLEMENATIONS OF THRESHOLD LOGIC FUNCTIONS. Comunicación en congreso. GLSVLSI (1.2001.DESCONOCIDO). DESCONOCIDO. 2001
Koegst-,M;Ruelke-,S;Susse-,H;Franke-,G;Avedillo-De, Maria Jose:
TWO-CRITERIAL CONSTRAIN-DRIVEN FSM STATE ENCODING FOR LOW POWER. Comunicación en congreso. EUROMICRO SYMPOSIUM ON DIGITAL SYSTEMS (1.2001.DESCONOCIDO). DESCONOCIDO. 2001
TWO-CRITERIAL CONSTRAIN-DRIVEN FSM STATE ENCODING FOR LOW POWER. Comunicación en congreso. EUROMICRO SYMPOSIUM ON DIGITAL SYSTEMS (1.2001.DESCONOCIDO). DESCONOCIDO. 2001
Martínez-Pérez, Manuel;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Koegst-,M;Ruelke-,S;Susse-,H:
NEW LOW POWER STATE ASSIGNMENT APPROACH. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DCIS 2000 (15.2000.MONTPELLIER, FRANCIA). MONTPELLIER, FRANCIA. 2000
NEW LOW POWER STATE ASSIGNMENT APPROACH. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DCIS 2000 (15.2000.MONTPELLIER, FRANCIA). MONTPELLIER, FRANCIA. 2000
Martínez-Pérez, Manuel;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Huertas-Diaz, Jose Luis:
NEW IDEAS ON FACE CONSTRAINED GENERATION. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DCIS 2000 (15.2000.MONTPELLIER, FRANCIA). MONTPELLIER, FRANCIA. 2000
NEW IDEAS ON FACE CONSTRAINED GENERATION. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DCIS 2000 (15.2000.MONTPELLIER, FRANCIA). MONTPELLIER, FRANCIA. 2000
Rueda-Rueda, Adoracion;Avedillo-De, Maria Jose;Guerra-,P.;Quintana-Toledo, Jose Maria;Serra-,F.;Vazquez-Garcia De La Vega, Diego;Yufera-Garcia, Alberto:
DISEÑO E IMPLEMENTACION DE UN BIOFONO DIGITAL CMOS DE BAJO CONSUMO. Comunicación en congreso. SEMINARIO DEL PROGRAMA NACIONAL DE TECNOLOGIAS DE LA INFORMACION Y LAS COMUNICACIONES (TEDEA2000). . 2000
DISEÑO E IMPLEMENTACION DE UN BIOFONO DIGITAL CMOS DE BAJO CONSUMO. Comunicación en congreso. SEMINARIO DEL PROGRAMA NACIONAL DE TECNOLOGIAS DE LA INFORMACION Y LAS COMUNICACIONES (TEDEA2000). . 2000
Koegst-,M;Ruelke-,S;Martínez-Pérez, Manuel;Susse-,H;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
COMBINATION OF TWO APPROACHES FOR LOW POWER DESIGN OF CONTROLLERS. Comunicación en congreso. INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (7.2000.GDYNIA, POLONIA). GDYNIA, POLONIA. 2000
COMBINATION OF TWO APPROACHES FOR LOW POWER DESIGN OF CONTROLLERS. Comunicación en congreso. INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (7.2000.GDYNIA, POLONIA). GDYNIA, POLONIA. 2000
Rodriguez-Villegas, Esther;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Rueda-Rueda, Adoracion:
EFFICIENT VMOS REALIZATION OF TRESHOLD VOTERS FOR SELF-PURGING REDUNDANCY. Comunicación en congreso. BRAZILIAN SYMPOSIUM ON INTEGRATED CIRCUIT DESIGN (13.2000.BRASIL). BRASIL. 2000
EFFICIENT VMOS REALIZATION OF TRESHOLD VOTERS FOR SELF-PURGING REDUNDANCY. Comunicación en congreso. BRAZILIAN SYMPOSIUM ON INTEGRATED CIRCUIT DESIGN (13.2000.BRASIL). BRASIL. 2000
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Rodriguez-Villegas, Esther;Rueda-Rueda, Adoracion:
VMOS-BASED COMPRESSOR DESIGNS. Comunicación en congreso. INTERNATIONAL CONFERENCE ON MICROELECTRONICS (1.2000.TEHERÁN). TEHERÁN. 2000
VMOS-BASED COMPRESSOR DESIGNS. Comunicación en congreso. INTERNATIONAL CONFERENCE ON MICROELECTRONICS (1.2000.TEHERÁN). TEHERÁN. 2000
Rodriguez-Villegas, Esther;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Huertas-Sánchez, Gloria;Rueda-Rueda, Adoracion:
VMOS-BASED SORTERS FOR MULTIPLIER IMPLEMENTATION. Comunicación en congreso. INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSETMS (32.1999.ORLANDO, FLORIDA). ORLANDO, FLORIDA. 1999
VMOS-BASED SORTERS FOR MULTIPLIER IMPLEMENTATION. Comunicación en congreso. INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSETMS (32.1999.ORLANDO, FLORIDA). ORLANDO, FLORIDA. 1999
Martínez-Pérez, Manuel;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Huertas-Diaz, Jose Luis:
AN ALGORITHM FOR FACE-CONSTRAINED ENCODING OF SYMBOLS USING MINIMUM CODE LENGTH. Comunicación en congreso. DESIGN, AUTOMATION AND TEST IN EUROPE (1.1999.MUNICH). MUNICH. 1999
AN ALGORITHM FOR FACE-CONSTRAINED ENCODING OF SYMBOLS USING MINIMUM CODE LENGTH. Comunicación en congreso. DESIGN, AUTOMATION AND TEST IN EUROPE (1.1999.MUNICH). MUNICH. 1999
Martínez-Pérez, Manuel;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Huertas-Diaz, Jose Luis:
PICOLA: A NOVEL COLUMN-BASED ALGORITHM FOR PARTIAL ENCODING PROBLEMS. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE, DCIS 98 (13.1998.MADRID). . 1998
PICOLA: A NOVEL COLUMN-BASED ALGORITHM FOR PARTIAL ENCODING PROBLEMS. Comunicación en congreso. DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS CONFERENCE, DCIS 98 (13.1998.MADRID). . 1998
Martínez-Pérez, Manuel;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Huertas-Diaz, Jose Luis:
A DYNAMIC MODEL FOR THE STATE ASSIGNMENT. Comunicación en congreso. DESIGN AUTOMATION AND TEST IN EUROPE (1.1998.PARIS). PARIS. 1998
A DYNAMIC MODEL FOR THE STATE ASSIGNMENT. Comunicación en congreso. DESIGN AUTOMATION AND TEST IN EUROPE (1.1998.PARIS). PARIS. 1998
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Parra-Fernández, María Del Pilar;Huertas-Diaz, Jose Luis:
OPTIMUM PLA FOLDING THROUGH BOOLEAN SATISFIABILITY. Comunicación en congreso. ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE () (.1995.JAPON). JAPON. 1995
OPTIMUM PLA FOLDING THROUGH BOOLEAN SATISFIABILITY. Comunicación en congreso. ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE () (.1995.JAPON). JAPON. 1995
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Rueda-Rueda, Adoracion;Baena-Oliva, Maria Carmen;Huertas-Diaz, Jose Luis:
PRACTICAL LOW-COST CMOS REALIZATION OF COMPLEX LOGIC FUNCTIONS. Comunicación en congreso. EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN () (.1995.ESTAMBUL, TURQUÍA). ESTAMBUL, TURQUÍA. 1995
PRACTICAL LOW-COST CMOS REALIZATION OF COMPLEX LOGIC FUNCTIONS. Comunicación en congreso. EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN () (.1995.ESTAMBUL, TURQUÍA). ESTAMBUL, TURQUÍA. 1995
Parra-Fernández, María Del Pilar;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
PLEGADO ÓPTIMO DE PLAS MEDIANTE SATISFACTORIEDAD BOOLEANA. Comunicación en congreso. IX Congreso de Diseño de Circuitos Integrados (.1994.GRAN CANARIA). GRAN CANARIA. 1994
PLEGADO ÓPTIMO DE PLAS MEDIANTE SATISFACTORIEDAD BOOLEANA. Comunicación en congreso. IX Congreso de Diseño de Circuitos Integrados (.1994.GRAN CANARIA). GRAN CANARIA. 1994
Quintana-Toledo, Jose Maria;Rueda-Rueda, Adoracion;Avedillo-De, Maria Jose;Baena-Oliva, Maria Carmen:
DISEÑO EFICIENTE DE UN ELEMENTO-C DE MULLER BASADO EN PUERTAS UMBRAL. Comunicación en congreso. IX Congreso de Diseño de Circuitos Integrados (.1994.GRAN CANARIA). GRAN CANARIA. 1994
DISEÑO EFICIENTE DE UN ELEMENTO-C DE MULLER BASADO EN PUERTAS UMBRAL. Comunicación en congreso. IX Congreso de Diseño de Circuitos Integrados (.1994.GRAN CANARIA). GRAN CANARIA. 1994
Artículos publicados
Jiménez, Manuel;Nuñez-Martínez, Juan;Shamsi, Jafar;Linares-Barranco, Bernabe;Avedillo-De, Maria Jose:
Experimental Demonstration of Coupled Differential Oscillator Networks for Versatile Applications. Frontiers in Neuroscience. 2023. Vol: 17. 10.3389/fnins.2023.1294954.
Experimental Demonstration of Coupled Differential Oscillator Networks for Versatile Applications. Frontiers in Neuroscience. 2023. Vol: 17. 10.3389/fnins.2023.1294954.
Jiménez, Manuel;Avedillo-De, Maria Jose;Linares-Barranco, Bernabe;Nuñez-Martínez, Juan:
Learning Algorithms for Oscillatory Neural Networks as Associative Memory for Pattern Recognition. Frontiers in Neuroscience. 2023. Vol: 17. 10.3389/fnins.2023.1257611.
Learning Algorithms for Oscillatory Neural Networks as Associative Memory for Pattern Recognition. Frontiers in Neuroscience. 2023. Vol: 17. 10.3389/fnins.2023.1257611.
Avedillo-De, Maria Jose;Jiménez, Manuel;Linares-Barranco, Bernabe;Nuñez-Martínez, Juan:
Operating Coupled VO2-based Oscillators for Solving Ising Models. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2023. 10.1109/JETCAS.2023.3328887.
Operating Coupled VO2-based Oscillators for Solving Ising Models. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2023. 10.1109/JETCAS.2023.3328887.
Abernot, Madeleine;Gil, Thierry;Jiménez, Manuel;Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Linares-Barranco, Bernabe;Gonos, Théophile;Hardelin, Tanguy;Todri-sanial, Aida:
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications. Frontiers in Neuroscience. 2021. https://doi.org/10.3389/fnins.2021.713054.
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications. Frontiers in Neuroscience. 2021. https://doi.org/10.3389/fnins.2021.713054.
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Jiménez, Manuel;Todri-sanial, Aida;Corti, Elisabetta;Karg, Siegfried;Linares-Barranco, Bernabe:
Insights into the Dynamics of VO2 Coupled Oscillators for ONNs. IEEE Transactions on Circuits and Systems. Part 2: Express Briefs. 2021. https://doi.org/10.1109/TCSII.2021.3085133.
Insights into the Dynamics of VO2 Coupled Oscillators for ONNs. IEEE Transactions on Circuits and Systems. Part 2: Express Briefs. 2021. https://doi.org/10.1109/TCSII.2021.3085133.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Jiménez, Manuel;Quintana-Toledo, Jose Maria;Todri-sanial, Aida;Corti, Elisabetta;Karg, Siegfried;Linares-Barranco, Bernabe:
Oscillatory Neural Networks Using VO2 Based Phase Encoded Logic. Frontiers in Neuroscience. 2021. https://doi.org/10.3389/fnins.2021.655823.
Oscillatory Neural Networks Using VO2 Based Phase Encoded Logic. Frontiers in Neuroscience. 2021. https://doi.org/10.3389/fnins.2021.655823.
Todri-sanial, Aida;Avedillo-De, Maria Jose;Linares-Barranco, Bernabe;Carapezzi, Stefania;Delacour, Corentin;Abernot, Madeleine;Gil, Thierry;Corti, Elisabetta;Karg, Siegfried;Nuñez-Martínez, Juan;Jiménez, Manuel:
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. IEEE Transactions on Neural Networks and Learning Systems. 2021.
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. IEEE Transactions on Neural Networks and Learning Systems. 2021.
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Nuñez-Martínez, Juan:
Phase Transition Device for Phase Storing. IEEE Transactions on Nanotechnology. 2020. Pág. 107-112. 10.1109/TNANO.2020.2965243.
Phase Transition Device for Phase Storing. IEEE Transactions on Nanotechnology. 2020. Pág. 107-112. 10.1109/TNANO.2020.2965243.
Jiménez, Manuel;Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Hybrid Phase Transition FET Devices for Logic Computation. IEEE Journal on Exploratory Solid-State Computatio. 2020. Vol: 6. Núm: 1. Pág. 1-8. 10.1109/JXCDC.2020.2993313.
Hybrid Phase Transition FET Devices for Logic Computation. IEEE Journal on Exploratory Solid-State Computatio. 2020. Vol: 6. Núm: 1. Pág. 1-8. 10.1109/JXCDC.2020.2993313.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Approaching the Design of Energy Recovery Logic Circuits using Tunnel Transistors. IEEE Transactions on Nanotechnology. 2020. Vol: 19. Pág. 500-507. 10.1109/TNANO.2020.3004941.
Approaching the Design of Energy Recovery Logic Circuits using Tunnel Transistors. IEEE Transactions on Nanotechnology. 2020. Vol: 19. Pág. 500-507. 10.1109/TNANO.2020.3004941.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Power and Speed Evaluation of Hyper-FET Circuits. IEEE Access. 2018. Vol: 7. Pág. 6724-6732. 10.1109/ACCESS.2018.2889016.
Power and Speed Evaluation of Hyper-FET Circuits. IEEE Access. 2018. Vol: 7. Pág. 6724-6732. 10.1109/ACCESS.2018.2889016.
Avedillo-De, Maria Jose;Jiménez, Manuel;Nuñez-Martínez, Juan:
Phase Transition FETs for Improved Dynamic Logic Gates. IEEE Electron Device Letters. 2018. Vol: 39. Núm: 11. Pág. 1776-1779. 10.1109/LED.2018.2871855.
Phase Transition FETs for Improved Dynamic Logic Gates. IEEE Electron Device Letters. 2018. Vol: 39. Núm: 11. Pág. 1776-1779. 10.1109/LED.2018.2871855.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications. IEEE Journal of the Electron Devices Society. 2017. Vol: 5. Núm: 6. Pág. 530-534. 10.1109/JEDS.2017.2737598.
Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications. IEEE Journal of the Electron Devices Society. 2017. Vol: 5. Núm: 6. Pág. 530-534. 10.1109/JEDS.2017.2737598.
Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Insights Into the Operation of Hyper-FET-Based Circuits. IEEE Transactions on Electron Devices. 2017. Vol: 64. Núm: 9. Pág. 3912-3918. 10.1109/TED.2017.2726765.
Insights Into the Operation of Hyper-FET-Based Circuits. IEEE Transactions on Electron Devices. 2017. Vol: 64. Núm: 9. Pág. 3912-3918. 10.1109/TED.2017.2726765.
Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Impact of the RT¿level architecture on the power performance of tunnel transistor circuits. International Journal of Circuit Theory and Applications. 2017. Vol: 46. Núm: 3. Pág. 647-655. https://doi.org/10.1002/cta.2398.
Impact of the RT¿level architecture on the power performance of tunnel transistor circuits. International Journal of Circuit Theory and Applications. 2017. Vol: 46. Núm: 3. Pág. 647-655. https://doi.org/10.1002/cta.2398.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs. IEEE Transactions on Nanotechnology. 2016. Vol: 16. Núm: 1. Pág. 83-89. 10.1109/TNANO.2016.2629264.
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs. IEEE Transactions on Nanotechnology. 2016. Vol: 16. Núm: 1. Pág. 83-89. 10.1109/TNANO.2016.2629264.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Comparative Analysis of Projected Tunnel and CMOS Transistors for Distinct Logic Applications Areas. IEEE Transactions on Electron Devices. 2016. Vol: 63. Núm: 12. Pág. 5012-5020. 10.1109/TED.2016.2616891.
Comparative Analysis of Projected Tunnel and CMOS Transistors for Distinct Logic Applications Areas. IEEE Transactions on Electron Devices. 2016. Vol: 63. Núm: 12. Pág. 5012-5020. 10.1109/TED.2016.2616891.
Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Improving speed of Tunnel FETs logic circuits. Electronics Letters. 2015. Vol: 51. Núm: 21. Pág. 1702-1704. 10.1049/el.2015.2416.
Improving speed of Tunnel FETs logic circuits. Electronics Letters. 2015. Vol: 51. Núm: 21. Pág. 1702-1704. 10.1049/el.2015.2416.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monoestable to Bistable Logic Elements. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014. Vol: 22. Núm: 10. Pág. 2238-2242. 10.1109/TVLSI.2013.2283306.
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monoestable to Bistable Logic Elements. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014. Vol: 22. Núm: 10. Pág. 2238-2242. 10.1109/TVLSI.2013.2283306.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Novel Pipeline Architectures based on Negative Differential Resistance Devices. Microelectronics Journal. 2013. Vol: 44. Núm: 9. Pág. 807-813. 10.1016/j.mejo.2013.06.012.
Novel Pipeline Architectures based on Negative Differential Resistance Devices. Microelectronics Journal. 2013. Vol: 44. Núm: 9. Pág. 807-813. 10.1016/j.mejo.2013.06.012.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Domino inspired MOBILE networks. Electronics Letters. 2012. Vol: 48. Núm: 5. Pág. 292-293.
Domino inspired MOBILE networks. Electronics Letters. 2012. Vol: 48. Núm: 5. Pág. 292-293.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Two-Phase RTD-CMOS Pipelined Circuits. IEEE Transactions on Nanotechnology. 2012. Vol: 11. Núm: 6. Pág. 1063-1069. 10.1109/TNANO.2012.2213839 .
Two-Phase RTD-CMOS Pipelined Circuits. IEEE Transactions on Nanotechnology. 2012. Vol: 11. Núm: 6. Pág. 1063-1069. 10.1109/TNANO.2012.2213839 .
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
IMPROVED NANOPIPELINED RTD ADDERS USING GENERALIZED THRESHOLD GATES. IEEE Transactions on Nanotechnology. 2011. Vol: 10. Núm: 1. Pág. 155-162.
IMPROVED NANOPIPELINED RTD ADDERS USING GENERALIZED THRESHOLD GATES. IEEE Transactions on Nanotechnology. 2011. Vol: 10. Núm: 1. Pág. 155-162.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Simplified single-phase clock scheme for MOBILE networks. Electronics Letters. 2011. Vol: 47. Núm: 11. Pág. 648-650.
Simplified single-phase clock scheme for MOBILE networks. Electronics Letters. 2011. Vol: 47. Núm: 11. Pág. 648-650.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
RTD-CMOS Pipelined Networks for Reduced Power Consumption. IEEE Transactions on Nanotechnology. 2011. Vol: 10. Núm: 6. Pág. 1217-1220.
RTD-CMOS Pipelined Networks for Reduced Power Consumption. IEEE Transactions on Nanotechnology. 2011. Vol: 10. Núm: 6. Pág. 1217-1220.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
EFFICIENT REALISATION OF MOS-NDR THRESHOLD LOGIC GATES. Electronics Letters. 2009. Vol: 45. Núm: 23. Pág. 1158-1160.
EFFICIENT REALISATION OF MOS-NDR THRESHOLD LOGIC GATES. Electronics Letters. 2009. Vol: 45. Núm: 23. Pág. 1158-1160.
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Pettenghi-Roldan, Hector;Nuñez-Martínez, Juan:
OPERATION LIMITS FOR RTD-BASED MOBILE CIRCUITS. IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2009. Vol: 56. Núm: 2. Pág. 350-363.
OPERATION LIMITS FOR RTD-BASED MOBILE CIRCUITS. IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2009. Vol: 56. Núm: 2. Pág. 350-363.
Romeira-,Bruno;Figueiredo-,Jose Maria;Slight-,T.J:;Wang-,L.M.;Wasige-,E.;Ironside-,C.N.;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
SYNCHRONISATION AND CHAOS IN A LASER DIODE DRIVEN BY A RESONANT TUNNELLING DIODE. IET Optoelectronics. 2008. Vol: 2. Núm: 6. Pág. 211-215.
SYNCHRONISATION AND CHAOS IN A LASER DIODE DRIVEN BY A RESONANT TUNNELLING DIODE. IET Optoelectronics. 2008. Vol: 2. Núm: 6. Pág. 211-215.
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
USING MULTI-THRESHOLD THRESHOLD GATES IN RTD-BASED LOGIC DESIGN: A CASE STUDY. Microelectronics Journal. 2008. Vol: 39. Núm: 2. Pág. 241-247.
USING MULTI-THRESHOLD THRESHOLD GATES IN RTD-BASED LOGIC DESIGN: A CASE STUDY. Microelectronics Journal. 2008. Vol: 39. Núm: 2. Pág. 241-247.
Pettenghi-Roldan, Hector;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
SINGLE PHASE CLOCK SCHEME FOR MOBILE LOGIC GATES. Electronics Letters. 2006. Vol: 42. Núm: 24. Pág. 1382-1383.
SINGLE PHASE CLOCK SCHEME FOR MOBILE LOGIC GATES. Electronics Letters. 2006. Vol: 42. Núm: 24. Pág. 1382-1383.
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Pettenghi-Roldan, Hector:
SELF-LATCHING OPERATION OF MOBILE CIRCUITS USING SERIES-CONNECTION OF RTDS AND TRANSISTORS. IEEE Transactions on Circuits and Systems Part II: Analog and Digital Signal Processing. 2006. Vol: 53. Núm: 5. Pág. 334-338.
SELF-LATCHING OPERATION OF MOBILE CIRCUITS USING SERIES-CONNECTION OF RTDS AND TRANSISTORS. IEEE Transactions on Circuits and Systems Part II: Analog and Digital Signal Processing. 2006. Vol: 53. Núm: 5. Pág. 334-338.
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Pettenghi-Roldan, Hector:
INCREASED LOGIC FUNCTIONALITY OF CLOCKED SERIES-CONNECTED RTDS. IEEE Transactions on Nanotechnology. 2006. Vol: 5. Núm: 5. Pág. 606-611.
INCREASED LOGIC FUNCTIONALITY OF CLOCKED SERIES-CONNECTED RTDS. IEEE Transactions on Nanotechnology. 2006. Vol: 5. Núm: 5. Pág. 606-611.
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
ANALYSIS OF FREQUENCY DIVIDER RTD CIRCUITS. IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2005. Vol: 52. Núm: 10. Pág. 2234-2247.
ANALYSIS OF FREQUENCY DIVIDER RTD CIRCUITS. IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2005. Vol: 52. Núm: 10. Pág. 2234-2247.
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
TRANSISTOR CRITICAL SIZING IN MOBILE FOLLOWER. Electronics Letters. 2005. Vol: 41. Núm: 10. Pág. 583-584.
TRANSISTOR CRITICAL SIZING IN MOBILE FOLLOWER. Electronics Letters. 2005. Vol: 41. Núm: 10. Pág. 583-584.
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Huertas-Diaz, Jose Luis:
SIMPLIFIED REED-MULLER EXPRESSIONS FOR RESIDUE THRESHOLD FUNCTIONS. Circuits, Systems and Signal Processing. 2004. Vol: 23. Núm: 1. Pág. 45-56.
SIMPLIFIED REED-MULLER EXPRESSIONS FOR RESIDUE THRESHOLD FUNCTIONS. Circuits, Systems and Signal Processing. 2004. Vol: 23. Núm: 1. Pág. 45-56.
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;El-Alami-,H;Jiménez-Calderón-,A.:
A PRACTICAL PARALLEL ARCHITECTURE FOR STACKS FILTERS. Journal of VLSI Signal Processing. 2004. Vol: 38. Núm: 2. Pág. 91-100.
A PRACTICAL PARALLEL ARCHITECTURE FOR STACKS FILTERS. Journal of VLSI Signal Processing. 2004. Vol: 38. Núm: 2. Pág. 91-100.
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Jiménez-Naharro, Raúl:
PASS-TRANSISTOR BASED IMPLEMENTATIONS OF THRESHOLD LOGIC GATES FOR WOS FILTERING. Microelectronics Journal. 2004. Vol: 35. Núm: 11. Pág. 869-873.
PASS-TRANSISTOR BASED IMPLEMENTATIONS OF THRESHOLD LOGIC GATES FOR WOS FILTERING. Microelectronics Journal. 2004. Vol: 35. Núm: 11. Pág. 869-873.
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;El-Alami-,H:
WEIGHTED ORDER STATISTICS FILTER FOR REAL-TIME SIGNAL PROCESSING APPLICATIONS BASED ON PASS TRANSISTOR LOGIC. IEE Proceedings. Circuits, Devices and Systems. 2004. Vol: 151. Núm: 1. Pág. 31-36.
WEIGHTED ORDER STATISTICS FILTER FOR REAL-TIME SIGNAL PROCESSING APPLICATIONS BASED ON PASS TRANSISTOR LOGIC. IEE Proceedings. Circuits, Devices and Systems. 2004. Vol: 151. Núm: 1. Pág. 31-36.
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
NONLINEAR DYNAMICS IN FREQUENCY DIVIDER RTD CIRCUITS. Electronics Letters. 2004. Vol: 40. Núm: 10. Pág. 586-587.
NONLINEAR DYNAMICS IN FREQUENCY DIVIDER RTD CIRCUITS. Electronics Letters. 2004. Vol: 40. Núm: 10. Pág. 586-587.
Beiu-,V;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
VLSI IMPLEMENTATIONS OF THRESHOLD LOGIC - A COMPREHENSIVE SURVEY. IEEE Transactions on Neural Networks. 2003. Vol: 14. Núm: 5. Pág. 1217-1243.
VLSI IMPLEMENTATIONS OF THRESHOLD LOGIC - A COMPREHENSIVE SURVEY. IEEE Transactions on Neural Networks. 2003. Vol: 14. Núm: 5. Pág. 1217-1243.
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Pettenghi-Roldan, Hector;Kelly-,R;Thompson-,C.J.:
MULTI-THRESHOLD THRESHOLD LOGIC CIRCUIT DESIGN USING RESONANT TUNNELLING DEVICES. Electronics Letters. 2003. Vol: 39. Núm: 21. Pág. 1502-1504.
MULTI-THRESHOLD THRESHOLD LOGIC CIRCUIT DESIGN USING RESONANT TUNNELLING DEVICES. Electronics Letters. 2003. Vol: 39. Núm: 21. Pág. 1502-1504.
Martínez-,N;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Huertas-Diaz, Jose Luis:
COPAS: A NEW ALGORITHM FOR THE PARTIAL INPUT ENCODING PROBLEM. VLSI Design. 2002. Vol: 14. Núm: 2. Pág. 171-181.
COPAS: A NEW ALGORITHM FOR THE PARTIAL INPUT ENCODING PROBLEM. VLSI Design. 2002. Vol: 14. Núm: 2. Pág. 171-181.
Rodriguez-Villegas, Esther;Huertas-Sánchez, Gloria;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Rueda-,A:
A PRACTICAL FLOATING-GATE MULLER-C ELEMENT USING VMOS THRESHOLD GATES. IEEE Transactions on Circuits and Systems Part II: Analog and Digital Signal Processing. 2001. Vol: 48. Núm: 1. Pág. 102-106.
A PRACTICAL FLOATING-GATE MULLER-C ELEMENT USING VMOS THRESHOLD GATES. IEEE Transactions on Circuits and Systems Part II: Analog and Digital Signal Processing. 2001. Vol: 48. Núm: 1. Pág. 102-106.
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Huertas-Diaz, Jose Luis:
EFFICIENT REALIZATION OF A THRESHOLD VOTER FOR SELF-PURGING REDUNDANCY. Journal of Electronic Testing. 2001. Vol: 17. Núm: 1. Pág. 69-73.
EFFICIENT REALIZATION OF A THRESHOLD VOTER FOR SELF-PURGING REDUNDANCY. Journal of Electronic Testing. 2001. Vol: 17. Núm: 1. Pág. 69-73.
Rodriguez-Villegas, Esther;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Huertas-Sánchez, Gloria;Rueda-,A:
NU MOS-BASED SORTER FOR ARITHMETIC APPLICATIONS. VLSI Design. 2000. Vol: 11. Núm: 2. Pág. 129-136.
NU MOS-BASED SORTER FOR ARITHMETIC APPLICATIONS. VLSI Design. 2000. Vol: 11. Núm: 2. Pág. 129-136.
Rodriguez-Villegas, Esther;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Rueda-,A:
SORTING NETWORKS IMPLEMENTED AS VMOS CIRCUITS. Electronics Letters. 1998. Vol: 34. Núm: 23. Pág. 2237-2238.
SORTING NETWORKS IMPLEMENTED AS VMOS CIRCUITS. Electronics Letters. 1998. Vol: 34. Núm: 23. Pág. 2237-2238.
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Rueda-,A:
LOW-COST BSA TECHNIQUE FOR THRESHOLD-LOGIC GATE BASED MULTIPLIER IMPLEMENTATIONS. Electronics Letters. 1997. Vol: 33. Núm: 12. Pág. 1028-1030.
LOW-COST BSA TECHNIQUE FOR THRESHOLD-LOGIC GATE BASED MULTIPLIER IMPLEMENTATIONS. Electronics Letters. 1997. Vol: 33. Núm: 12. Pág. 1028-1030.
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Huertas-Diaz, Jose Luis:
Efficient State Reduction Methods for PLA-based Sequential Circuits. IEEE Proceedings. Computers and Digital Techniques. 1992. Vol: 139. Pág. 491-500.
Efficient State Reduction Methods for PLA-based Sequential Circuits. IEEE Proceedings. Computers and Digital Techniques. 1992. Vol: 139. Pág. 491-500.
Huertas-Diaz, Jose Luis;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
Area Optimised Registers by Using a Folded PLA. IEE Proceedings. Circuits, Devices and Systems. 1990. Vol: 137. Pág. 28-32.
Area Optimised Registers by Using a Folded PLA. IEE Proceedings. Circuits, Devices and Systems. 1990. Vol: 137. Pág. 28-32.
Tesis dirigidas o codirigidas
(Doctorando no grabado):
DESARROLLO Y EVALUACIÓN DE ARQUITECTURAS LÓGICAS BASADAS EN NANOPIPELINE. Tesis Doctoral. 2018
DESARROLLO Y EVALUACIÓN DE ARQUITECTURAS LÓGICAS BASADAS EN NANOPIPELINE. Tesis Doctoral. 2018
Nuñez-Martínez, Juan:
Diseño lógico de circuitos digitales usando dispositivos con característica NDR. Tesis Doctoral. 2011
Diseño lógico de circuitos digitales usando dispositivos con característica NDR. Tesis Doctoral. 2011
Pettenghi-Roldan, Hector:
UNA APORTACION AL DISEÑO DIGITAL USANDO DISPOSITIVOS BASADOS EN EFECTO TUNEY RESONANTE. Tesis Doctoral. 2009
UNA APORTACION AL DISEÑO DIGITAL USANDO DISPOSITIVOS BASADOS EN EFECTO TUNEY RESONANTE. Tesis Doctoral. 2009
Martínez-Pérez, Manuel:
ALGORITMOS DE CODIFICACIÓN BINARIA DE SÍMBOLOS PARA LA SÍNTESIS LÓGICA DE CIRCUITOS INTEGRADOS DIGITALES. Tesis Doctoral. 2003
ALGORITMOS DE CODIFICACIÓN BINARIA DE SÍMBOLOS PARA LA SÍNTESIS LÓGICA DE CIRCUITOS INTEGRADOS DIGITALES. Tesis Doctoral. 2003
