Directorio
JUAN NUÑEZ MARTINEZ
Categoría
FEDER US EMERGENTES
Departamento
Área
Electrónica
Centro
Docencia
Asignaturas que imparte
Investigación
Grupo de investigación
DISEÑO Y TEST DE CIRCUITOS INTEGRADOS DE SEÑAL MIXTA (DISEÑO Y TEST DE CIRCUITOS INT)
Proyectos y contratos de investigación
DISEÑO E IMPLEMENTACIÓN DE CIRCUITOS NANO-MICROELECTRÓNICOS USANDO DISPOSITIVOS CON CARACTERÍSTICAS NDR (TEC2007-67245/MIC - Investigador/a)
DISEÑO E IMPLEMENTACIÓN DE CIRCUITOS MULTIVALUADOS USANDO DISPOSITIVOS CON CARACTERÍSTICA NDR (P07-TIC-02961 - Investigador/a)
AYUDA A LA CONSOLIDACION DE GRUPOS DE INVESTIGACION - TIC 178 (CONVOCATORIA 2007) (P-2008/560 - Investigador/a)
AYUDA A LA CONSOLIDACION DE GRUPOS DE INVESTIGACION - TIC 178 CONVOCATORIA 2008 (2009/00000431 - Investigador/a)
AYUDA A LA CONSOLIDACION DE GRUPOS DE INVESTIGACIÓN.- TIC 178 CONVOCATORIA 2009 (2009/00001257 - Investigador/a)
ARQUITECTURAS Y CIRCUITOS CON RTDS PARA APLICACIONES LÓGICAS Y NO LINEALES (TEC2010/18937 - Investigador/a)
Power, reliability and security challenges in advanced CMOS and beyond-CMOS devices and circuits (RESURGENCE) (US-1380876 - Investigador Principal Joven)
Circuitos y Arquitecturas con Dispositivos Steep Slope para Aplicaciones de muy Bajo Consumo de Potencia (TEC2017-87052-P - Investigador/a)
Nano-Arquitecturas para Computación Lógica Usando Dispositivos Emergentes (TEC2013-40670-P - Investigador/a)
RADIATION TOLERANT ANALOGUE MIXED SIGNAL TECHNOLOGY SURVEY AND TEST VEHICLE DESIGN (Participante)
Capítulos en Libros
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
ANALYTIC APPROACH TO THE OPERATION OF RTD TERNARY INVERTERS BASED ON MML. Pág. 97-112. IN-TECH. IN-TECH. 2010.
ANALYTIC APPROACH TO THE OPERATION OF RTD TERNARY INVERTERS BASED ON MML. Pág. 97-112. IN-TECH. IN-TECH. 2010.
Asistencia a congresos
Jiménez, Manuel;Nuñez-Martínez, Juan;Shamsi, Jafar;Linares-Barranco, Bernabe;Avedillo-De, Maria Jose:
Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks. Comunicación en congreso. XXXVIII Conference on Design of Circuits and Integrated Systems. Málaga, Spain. 2023
Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks. Comunicación en congreso. XXXVIII Conference on Design of Circuits and Integrated Systems. Málaga, Spain. 2023
Jiménez, Manuel;Avedillo-De, Maria Jose;Linares-Barranco, Bernabe;Nuñez-Martínez, Juan:
Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory. Comunicación en congreso. XXXVIII Conference on Design of Circuits and Integrated Systems. Málaga, Spain. 2023
Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory. Comunicación en congreso. XXXVIII Conference on Design of Circuits and Integrated Systems. Málaga, Spain. 2023
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Jiménez, Manuel:
Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. Comunicación en congreso. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Funchal, Madeira, Portugal. 2023
Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. Comunicación en congreso. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Funchal, Madeira, Portugal. 2023
Jiménez, Manuel;Avedillo-De, Maria Jose;Nuñez-Martínez, Juan;Linares-Barranco, Bernabe:
Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. Comunicación en congreso. 2022 XXXVII IEEE Conference on Design of Circuits and Integrated Systems (DCIS). Pamplona, Navarra, España. 2022
Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. Comunicación en congreso. 2022 XXXVII IEEE Conference on Design of Circuits and Integrated Systems (DCIS). Pamplona, Navarra, España. 2022
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Jiménez, Manuel:
Solving Combinatorial Optimization Problems with Coupled Phase Transition based Oscillators. Comunicación en congreso. 2022 XXXVII IEEE Conference on Design of Circuits and Integrated Systems (DCIS). Pamplona, Navarra, España. 2022
Solving Combinatorial Optimization Problems with Coupled Phase Transition based Oscillators. Comunicación en congreso. 2022 XXXVII IEEE Conference on Design of Circuits and Integrated Systems (DCIS). Pamplona, Navarra, España. 2022
Nuñez-Martínez, Juan;Jiménez, Manuel;Avedillo-De, Maria Jose:
FeFETs for Phase Encoded Oscillatory based computing. Comunicación en congreso. 2021 XXXVI IEEE Conference on Design of Circuits and Integrated Systems (DCIS),. Vila Do Conde, Oporto, Portugal. 2021
FeFETs for Phase Encoded Oscillatory based computing. Comunicación en congreso. 2021 XXXVI IEEE Conference on Design of Circuits and Integrated Systems (DCIS),. Vila Do Conde, Oporto, Portugal. 2021
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Steep-slope Devices for Power Efficient Adiabatic Logic Circuits. Comunicación en congreso. XXXV Conference on Design of Circuits and Integrated Systems. Segovia. 2020
Steep-slope Devices for Power Efficient Adiabatic Logic Circuits. Comunicación en congreso. XXXV Conference on Design of Circuits and Integrated Systems. Segovia. 2020
Jiménez, Manuel;Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
An Approach to the Device-Circuit Co-Design of HyperFET Circuits. Comunicación en congreso. International Symposium on Circuits and Systems. Sevilla, España. 2020
An Approach to the Device-Circuit Co-Design of HyperFET Circuits. Comunicación en congreso. International Symposium on Circuits and Systems. Sevilla, España. 2020
Nuñez-Martínez, Juan;Jiménez, Manuel;Avedillo-De, Maria Jose:
Device circuit co-design of HyperFET transistors. Comunicación en congreso. 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS). BILBAO (ESPAÑA). 2019
Device circuit co-design of HyperFET transistors. Comunicación en congreso. 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS). BILBAO (ESPAÑA). 2019
Nuñez-Martínez, Juan;Roca, E.;Castro-López, Rafael;Martin-martinez, Javier;Rodriguez, Rosana;Nafria, Montserrat;Fernandez-Fernandez, Francisco V.:
Experimental Characterization of Time-Dependent Variability in Ring Oscillators. Comunicación en congreso. 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). Lausanne, ALPINE CENTER PIORA, SWITZERLAND. 2019
Experimental Characterization of Time-Dependent Variability in Ring Oscillators. Comunicación en congreso. 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). Lausanne, ALPINE CENTER PIORA, SWITZERLAND. 2019
Martín, Pablo;Nuñez-Martínez, Juan;Roca, E.;Castro-López, Rafael;Martin-martinez, Javier;Rodriguez, Rosana;Nafria, Montserrat;Fernandez-Fernandez, Francisco V.:
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks. Comunicación en congreso. 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). Lausanne, ALPINE CENTER PIORA, SWITZERLAND. 2019
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks. Comunicación en congreso. 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). Lausanne, ALPINE CENTER PIORA, SWITZERLAND. 2019
Tena-Sánchez, Erica;Delgado-lozano, Ignacio M.;Nuñez-Martínez, Juan;Acosta-Jimenez, Antonio Jose:
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. Comunicación en congreso. XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS . - Lyon, Francia, Francia. 2018
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. Comunicación en congreso. XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS . - Lyon, Francia, Francia. 2018
Quintero-Alvarez, Héctor Javier;Jiménez, Manuel;Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Inverting versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. Comunicación en congreso. 15TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN. - Praga, República Checa. 2018
Inverting versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. Comunicación en congreso. 15TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN. - Praga, República Checa. 2018
Saraza-canflanca, Pablo;Rodriguez, Rosana;Nafria, Montserrat;Fernandez-Fernandez, Francisco V.;Malagon, Daniel;Moreira, Fabio ;Toro-frías, Antonio;Nuñez-Martínez, Juan;Castro-López, Rafael;Roca, E.;Diaz-fortuny, Javier;Martin-martinez, Javier:
Design considerations of an SRAM array for the statistical validation of time-dependent variability models. Comunicación en congreso. 15TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN. - Praga, República Checa. 2018
Design considerations of an SRAM array for the statistical validation of time-dependent variability models. Comunicación en congreso. 15TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN. - Praga, República Checa. 2018
Fiorelli-Martegani, Rafaella Bianca;Nuñez-Martínez, Juan;Silveira, Fernando :
All-Inversion Region gm/Id Methodology for RF Circuits in FinFET Technologies. Comunicación en congreso. 16th IEEE International NEWCAS Conference. - Montreal, Canadá. 2018
All-Inversion Region gm/Id Methodology for RF Circuits in FinFET Technologies. Comunicación en congreso. 16th IEEE International NEWCAS Conference. - Montreal, Canadá. 2018
Nuñez-Martínez, Juan:
Impact of TFET Reverse Currents Into Circuit Operation: A Case Study. Comunicación en congreso. 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Granada. 2018
Impact of TFET Reverse Currents Into Circuit Operation: A Case Study. Comunicación en congreso. 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Granada. 2018
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Exploring Logic Architectures Suitable for TFETs Devices. Comunicación en congreso. 2017 IEEE International Symposium on Circuits and Systems (ISCAS). Baltimore, MD, USA. 2017
Exploring Logic Architectures Suitable for TFETs Devices. Comunicación en congreso. 2017 IEEE International Symposium on Circuits and Systems (ISCAS). Baltimore, MD, USA. 2017
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Complementary Tunnel Gate Topology to Reduce Crosstalk Effects. Comunicación en congreso. XXXI CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS DCIS 2016. GRANADA. 2016
Complementary Tunnel Gate Topology to Reduce Crosstalk Effects. Comunicación en congreso. XXXI CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS DCIS 2016. GRANADA. 2016
Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits. Comunicación en congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). BREMEN, ALEMANIA. 2016
Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits. Comunicación en congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). BREMEN, ALEMANIA. 2016
Tena-Sánchez, Erica;Acosta-Jimenez, Antonio Jose;Nuñez-Martínez, Juan:
Secure Cryptographic Hardware Implementation Issues for High-Performance Applications. Poster en Congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). BREMEN, ALEMANIA. 2016
Secure Cryptographic Hardware Implementation Issues for High-Performance Applications. Poster en Congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). BREMEN, ALEMANIA. 2016
Nuñez-Martínez, Juan;Gines-Arteaga, Antonio Jose;Peralias-Macias, Eduardo;Rueda-Rueda, Adoracion:
Low-jitter differential clock driver circuits for high-performance high-resolution ADCs. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. ESTORIL (PORTUGAL). 2015
Low-jitter differential clock driver circuits for high-performance high-resolution ADCs. Comunicación en congreso. DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. ESTORIL (PORTUGAL). 2015
Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Assessing application areas for tunnel transistor technologies. Comunicación en congreso. Design of Integrated Circuits and Systems 2015. Lisboa. 2015
Assessing application areas for tunnel transistor technologies. Comunicación en congreso. Design of Integrated Circuits and Systems 2015. Lisboa. 2015
Quintero-Alvarez, Héctor Javier;Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Improving robustness of dynamic logic based pipelines. Comunicación en congreso. Design of Circuits and Integrated Systems 2015. . 2015
Improving robustness of dynamic logic based pipelines. Comunicación en congreso. Design of Circuits and Integrated Systems 2015. . 2015
Nuñez-Martínez, Juan;Gines-Arteaga, Antonio Jose;Peralias-Macias, Eduardo;Rueda-Rueda, Adoracion:
An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. Comunicación en congreso. IEEE 6th Latin American Symposium on Circuits & Systems. BUENOS AIRES (ARGENTINA)-MONTEVIDEO (URUGUAY). 2015
An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. Comunicación en congreso. IEEE 6th Latin American Symposium on Circuits & Systems. BUENOS AIRES (ARGENTINA)-MONTEVIDEO (URUGUAY). 2015
Nuñez-Martínez, Juan;Quintero-Alvarez, Héctor Javier;Avedillo-De, Maria Jose:
DOE based high-performance gate-level pipelines. Comunicación en congreso. Powe and Timming Modeling, Optimization and Simulation International Workshop. Palma de Mallorca. 2014
DOE based high-performance gate-level pipelines. Comunicación en congreso. Powe and Timming Modeling, Optimization and Simulation International Workshop. Palma de Mallorca. 2014
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Quintero-Alvarez, Héctor Javier:
Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. . 2013
Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. . 2013
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Novel dynamic gate topology for superpipelines in DSM technologies. Comunicación en congreso. Digital System Design EUROMICRO. Santander. 2013
Novel dynamic gate topology for superpipelines in DSM technologies. Comunicación en congreso. Digital System Design EUROMICRO. Santander. 2013
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IEEE International Conference on Electronics, Circuits, and Systems . SEVILLA, ESPAÑA. 2012
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IEEE International Conference on Electronics, Circuits, and Systems . SEVILLA, ESPAÑA. 2012
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications. Comunicación en congreso. International Workshop on Power and Timing Modeling, Optimization and Simulation . NEWCASTLE, REINO UNIDO, United Kingdom. 2012
Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications. Comunicación en congreso. International Workshop on Power and Timing Modeling, Optimization and Simulation . NEWCASTLE, REINO UNIDO, United Kingdom. 2012
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Compact and Power Efficient MOS-NDR Muller C-Elements. Comunicación en congreso. Doctoral Conference on Computing, Electrical and Industrial Systems. CAPARICA (LISBOA). 2012
Compact and Power Efficient MOS-NDR Muller C-Elements. Comunicación en congreso. Doctoral Conference on Computing, Electrical and Industrial Systems. CAPARICA (LISBOA). 2012
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IBERCHIP 2012. PLAYA DEL CARMEN, MEXICO. 2012
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IBERCHIP 2012. PLAYA DEL CARMEN, MEXICO. 2012
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs. Comunicación en congreso. SPIE 2011. PRAGA, REPÚBLICA CHECA. 2011
Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs. Comunicación en congreso. SPIE 2011. PRAGA, REPÚBLICA CHECA. 2011
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Efficient Realization of RTD-CMOS Logic Gates. Comunicación en congreso. Great Lakes Symposium on VLSI. LAUSSANE, SUIZA. 2011
Efficient Realization of RTD-CMOS Logic Gates. Comunicación en congreso. Great Lakes Symposium on VLSI. LAUSSANE, SUIZA. 2011
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
EVALUATION OF RTD-CMOS LOGIC GATES. Comunicación en congreso. DSD EUROMICRO 2010 () (.2010.LILLE, FRANCIA). LILLE, FRANCIA. 2010
EVALUATION OF RTD-CMOS LOGIC GATES. Comunicación en congreso. DSD EUROMICRO 2010 () (.2010.LILLE, FRANCIA). LILLE, FRANCIA. 2010
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
SINGLE PHASE MOS-NDR MOBILE NETWORKS. Comunicación en congreso. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1979-1982, Jun. 2010. PARIS, FRANCE. 2010
SINGLE PHASE MOS-NDR MOBILE NETWORKS. Comunicación en congreso. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1979-1982, Jun. 2010. PARIS, FRANCE. 2010
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
REDES MOBILE MOS-NDR OPERANDO CON RELOJ DE UNA FASE. Comunicación en congreso. IBERCHIP 2010 () (.2010.IGUAZÚ (BRASIL)). IGUAZÚ (BRASIL). 2010
REDES MOBILE MOS-NDR OPERANDO CON RELOJ DE UNA FASE. Comunicación en congreso. IBERCHIP 2010 () (.2010.IGUAZÚ (BRASIL)). IGUAZÚ (BRASIL). 2010
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
DC OPERATION LIMITS FOR MOBILE INVERTERS. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (24) (24.2009.Zaragoza). Zaragoza. 2009
DC OPERATION LIMITS FOR MOBILE INVERTERS. Comunicación en congreso. CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (24) (24.2009.Zaragoza). Zaragoza. 2009
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
MULLER C-ELEMENTS MULTIENTRADA BASADOS EN MOS-NDR. Comunicación en congreso. IBERCHIP () (.2009.BUENOS AIRES, ARGENTINA). BUENOS AIRES, ARGENTINA. 2009
MULLER C-ELEMENTS MULTIENTRADA BASADOS EN MOS-NDR. Comunicación en congreso. IBERCHIP () (.2009.BUENOS AIRES, ARGENTINA). BUENOS AIRES, ARGENTINA. 2009
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Pettenghi-Roldan, Hector;Nuñez-Martínez, Juan:
PUERTAS UMBRAL GENERALIZADAS PARA EL DISEÑO LÓGICOS DE CIRCUITOS MOBILE. Comunicación en congreso. IBERCHIP () (.2009.BUENOS AIRES, ARGENTINA). BUENOS AIRES, ARGENTINA. 2009
PUERTAS UMBRAL GENERALIZADAS PARA EL DISEÑO LÓGICOS DE CIRCUITOS MOBILE. Comunicación en congreso. IBERCHIP () (.2009.BUENOS AIRES, ARGENTINA). BUENOS AIRES, ARGENTINA. 2009
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
FAST AND AREA EFFICIENT MULTI-INPUT MULLER C-ELEMENT BASED ON MOS-NDR. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS () (.2009.TAIPEI, TAIWAN). TAIPEI, TAIWAN. 2009
FAST AND AREA EFFICIENT MULTI-INPUT MULLER C-ELEMENT BASED ON MOS-NDR. Comunicación en congreso. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS () (.2009.TAIPEI, TAIWAN). TAIPEI, TAIWAN. 2009
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
LIMITS TO A CORRECT OPERATION IN RTD-BASED TERNARY INVERTERS. Comunicación en congreso. ISCAS 2008 () (.2008.SEATTLE, WASHINGTON, USA). SEATTLE, WASHINGTON, USA. 2008
LIMITS TO A CORRECT OPERATION IN RTD-BASED TERNARY INVERTERS. Comunicación en congreso. ISCAS 2008 () (.2008.SEATTLE, WASHINGTON, USA). SEATTLE, WASHINGTON, USA. 2008
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
DESIGN OF RTD-BASED NMIN/NMAX GATES. Comunicación en congreso. IEEE NANO 2008 () (.2008.ARLINGTONG, TX, USA). ARLINGTONG, TX, USA. 2008
DESIGN OF RTD-BASED NMIN/NMAX GATES. Comunicación en congreso. IEEE NANO 2008 () (.2008.ARLINGTONG, TX, USA). ARLINGTONG, TX, USA. 2008
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
A QUASI DIFFERENTIAL QUANTIZER BASED ON SMOBILE. Comunicación en congreso. IEEE SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (20) (20.2007.RÍO DE JANEIRO (BRAZIL)). RÍO DE JANEIRO (BRAZIL). 2008
A QUASI DIFFERENTIAL QUANTIZER BASED ON SMOBILE. Comunicación en congreso. IEEE SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (20) (20.2007.RÍO DE JANEIRO (BRAZIL)). RÍO DE JANEIRO (BRAZIL). 2008
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
ANALYTIC APPROACH TO THE OPERATION OF RTD TERNARY INVERTERS BASED ON MML. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POST-BINARY ULSI SYSTEMS (16) (16.2007.OSLO (NORWAY)). OSLO (NORWAY). 2007
ANALYTIC APPROACH TO THE OPERATION OF RTD TERNARY INVERTERS BASED ON MML. Comunicación en congreso. INTERNATIONAL WORKSHOP ON POST-BINARY ULSI SYSTEMS (16) (16.2007.OSLO (NORWAY)). OSLO (NORWAY). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
LIMITS TO A CORRECT EVALUATION IN RTD-BASED QUATERNARY INVERTERS. Comunicación en congreso. INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (37) (37.2007.OSLO (NORWAY)). OSLO (NORWAY). 2007
LIMITS TO A CORRECT EVALUATION IN RTD-BASED QUATERNARY INVERTERS. Comunicación en congreso. INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (37) (37.2007.OSLO (NORWAY)). OSLO (NORWAY). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
OPERATION LIMITS IN RTD-BASED TERNARY QUANTIZERS. Comunicación en congreso. ACM GREAT LAKES SYMPOSIUM ON VLSI (17) (17.2007.STRESSA-LAGO MAGGIORE (ITALY)). STRESSA-LAGO MAGGIORE (ITALY). 2007
OPERATION LIMITS IN RTD-BASED TERNARY QUANTIZERS. Comunicación en congreso. ACM GREAT LAKES SYMPOSIUM ON VLSI (17) (17.2007.STRESSA-LAGO MAGGIORE (ITALY)). STRESSA-LAGO MAGGIORE (ITALY). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
DC OPERATION LIMITS OF RTD TERNARY INVERTERS BASED ON NML. Comunicación en congreso. DCIS () (.2007.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2007
DC OPERATION LIMITS OF RTD TERNARY INVERTERS BASED ON NML. Comunicación en congreso. DCIS () (.2007.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
CORRECT DC OPERATION IN RTD BASED TERNARY INVERTERS. Comunicación en congreso. IEEE INTERNATIONAL CONFERENCE OF NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS (2) (2.2007.BANGKOK (THAILANDIA)). BANGKOK (THAILANDIA). 2007
CORRECT DC OPERATION IN RTD BASED TERNARY INVERTERS. Comunicación en congreso. IEEE INTERNATIONAL CONFERENCE OF NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS (2) (2.2007.BANGKOK (THAILANDIA)). BANGKOK (THAILANDIA). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
CORRECT OPERATION IN SMOBILE-BASED QUASI-DIFFERENTIAL QUANTIZIERS. Comunicación en congreso. ECCTD 2007 () (.2007.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2007
CORRECT OPERATION IN SMOBILE-BASED QUASI-DIFFERENTIAL QUANTIZIERS. Comunicación en congreso. ECCTD 2007 () (.2007.SEVILLA, ESPAÑA). Santander (ESPAÑA). 2007
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
HOLDING PRESERVING IN RTD-BASED MULTIPLE-VALUED QUANTIZIERS. Comunicación en congreso. IEEE CONFERENCE ON NANOTECHNOLOGY (7) (7.2007.HONG-KONG (CHINA)). HONG-KONG (CHINA). 2007
HOLDING PRESERVING IN RTD-BASED MULTIPLE-VALUED QUANTIZIERS. Comunicación en congreso. IEEE CONFERENCE ON NANOTECHNOLOGY (7) (7.2007.HONG-KONG (CHINA)). HONG-KONG (CHINA). 2007
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
DC CORRECT OPERATION IN MOBILE INVERTERS. Comunicación en congreso. MWCAS 2006 (49) (49.2006.SAN JUAN (PUERTO RICO)). SAN JUAN (PUERTO RICO). 2006
DC CORRECT OPERATION IN MOBILE INVERTERS. Comunicación en congreso. MWCAS 2006 (49) (49.2006.SAN JUAN (PUERTO RICO)). SAN JUAN (PUERTO RICO). 2006
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
LIMITS TO A CORRECT EVALUATION IN RTD BASED TERNARY INVERTERS. Comunicación en congreso. ICECS () (.2006.NICE (FRANCE)). NICE (FRANCE). 2006
LIMITS TO A CORRECT EVALUATION IN RTD BASED TERNARY INVERTERS. Comunicación en congreso. ICECS () (.2006.NICE (FRANCE)). NICE (FRANCE). 2006
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
HOLDING DISSAPEARANCE IN RTD-BASED QUANTIZERS. Comunicación en congreso. ENS 2006 () (.2006.PARIS). PARIS. 2006
HOLDING DISSAPEARANCE IN RTD-BASED QUANTIZERS. Comunicación en congreso. ENS 2006 () (.2006.PARIS). PARIS. 2006
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose:
OPERATION LIMITS FOR MOBILE FOLLOWER. Comunicación en congreso. NANO 2006 (6) (6.2006.CINCINNATI). CINCINNATI. 2006
OPERATION LIMITS FOR MOBILE FOLLOWER. Comunicación en congreso. NANO 2006 (6) (6.2006.CINCINNATI). CINCINNATI. 2006
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
DESIGN GUIDES FOR A CORRECT DC OPERATION IN RTD-BASED THRESHOLD GATES. Comunicación en congreso. IEEE EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN () (.2006.CAVTAT, CROACIA). CAVTAT, CROACIA. 2006
DESIGN GUIDES FOR A CORRECT DC OPERATION IN RTD-BASED THRESHOLD GATES. Comunicación en congreso. IEEE EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN () (.2006.CAVTAT, CROACIA). CAVTAT, CROACIA. 2006
Artículos publicados
Jiménez, Manuel;Nuñez-Martínez, Juan;Shamsi, Jafar;Linares-Barranco, Bernabe;Avedillo-De, Maria Jose:
Experimental Demonstration of Coupled Differential Oscillator Networks for Versatile Applications. Frontiers in Neuroscience. 2023. Vol: 17. 10.3389/fnins.2023.1294954.
Experimental Demonstration of Coupled Differential Oscillator Networks for Versatile Applications. Frontiers in Neuroscience. 2023. Vol: 17. 10.3389/fnins.2023.1294954.
Jiménez, Manuel;Avedillo-De, Maria Jose;Linares-Barranco, Bernabe;Nuñez-Martínez, Juan:
Learning Algorithms for Oscillatory Neural Networks as Associative Memory for Pattern Recognition. Frontiers in Neuroscience. 2023. Vol: 17. 10.3389/fnins.2023.1257611.
Learning Algorithms for Oscillatory Neural Networks as Associative Memory for Pattern Recognition. Frontiers in Neuroscience. 2023. Vol: 17. 10.3389/fnins.2023.1257611.
Avedillo-De, Maria Jose;Jiménez, Manuel;Linares-Barranco, Bernabe;Nuñez-Martínez, Juan:
Operating Coupled VO2-based Oscillators for Solving Ising Models. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2023. 10.1109/JETCAS.2023.3328887.
Operating Coupled VO2-based Oscillators for Solving Ising Models. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2023. 10.1109/JETCAS.2023.3328887.
Delgado -lozano, Ignacio M;Acosta-Jimenez, Antonio Jose;Tena-Sánchez, Erica;Nuñez-Martínez, Juan:
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. IEEE Embedded Systems Letters. 2022. Vol: 14. Núm: 2. Pág. 99-102. 10.1109/LES.2021.3122395.
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. IEEE Embedded Systems Letters. 2022. Vol: 14. Núm: 2. Pág. 99-102. 10.1109/LES.2021.3122395.
Abernot, Madeleine;Gil, Thierry;Jiménez, Manuel;Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Linares-Barranco, Bernabe;Gonos, Théophile;Hardelin, Tanguy;Todri-sanial, Aida:
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications. Frontiers in Neuroscience. 2021. https://doi.org/10.3389/fnins.2021.713054.
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications. Frontiers in Neuroscience. 2021. https://doi.org/10.3389/fnins.2021.713054.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Jiménez, Manuel;Quintana-Toledo, Jose Maria;Todri-sanial, Aida;Corti, Elisabetta;Karg, Siegfried;Linares-Barranco, Bernabe:
Oscillatory Neural Networks Using VO2 Based Phase Encoded Logic. Frontiers in Neuroscience. 2021. https://doi.org/10.3389/fnins.2021.655823.
Oscillatory Neural Networks Using VO2 Based Phase Encoded Logic. Frontiers in Neuroscience. 2021. https://doi.org/10.3389/fnins.2021.655823.
Todri-sanial, Aida;Avedillo-De, Maria Jose;Linares-Barranco, Bernabe;Carapezzi, Stefania;Delacour, Corentin;Abernot, Madeleine;Gil, Thierry;Corti, Elisabetta;Karg, Siegfried;Nuñez-Martínez, Juan;Jiménez, Manuel:
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. IEEE Transactions on Neural Networks and Learning Systems. 2021.
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. IEEE Transactions on Neural Networks and Learning Systems. 2021.
Nuñez-Martínez, Juan;Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Jiménez, Manuel;Todri-sanial, Aida;Corti, Elisabetta;Karg, Siegfried;Linares-Barranco, Bernabe:
Insights into the Dynamics of VO2 Coupled Oscillators for ONNs. IEEE Transactions on Circuits and Systems. Part 2: Express Briefs. 2021. https://doi.org/10.1109/TCSII.2021.3085133.
Insights into the Dynamics of VO2 Coupled Oscillators for ONNs. IEEE Transactions on Circuits and Systems. Part 2: Express Briefs. 2021. https://doi.org/10.1109/TCSII.2021.3085133.
Delgado-lozano, Ignacio M.;Tena-Sánchez, Erica;Nuñez-Martínez, Juan;Acosta-Jimenez, Antonio Jose:
Design and analysis of secure emerging crypto-hardware using HyperFET devices. IEEE Transactions on Emerging Topics in Computing. 2020. Vol: Online. 10.1109/TETC.2020.2977735.
Design and analysis of secure emerging crypto-hardware using HyperFET devices. IEEE Transactions on Emerging Topics in Computing. 2020. Vol: Online. 10.1109/TETC.2020.2977735.
Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria;Nuñez-Martínez, Juan:
Phase Transition Device for Phase Storing. IEEE Transactions on Nanotechnology. 2020. Pág. 107-112. 10.1109/TNANO.2020.2965243.
Phase Transition Device for Phase Storing. IEEE Transactions on Nanotechnology. 2020. Pág. 107-112. 10.1109/TNANO.2020.2965243.
Jiménez, Manuel;Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Hybrid Phase Transition FET Devices for Logic Computation. IEEE Journal on Exploratory Solid-State Computatio. 2020. Vol: 6. Núm: 1. Pág. 1-8. 10.1109/JXCDC.2020.2993313.
Hybrid Phase Transition FET Devices for Logic Computation. IEEE Journal on Exploratory Solid-State Computatio. 2020. Vol: 6. Núm: 1. Pág. 1-8. 10.1109/JXCDC.2020.2993313.
Delgado-lozano, I. M.;Tena-Sánchez, Erica;Nuñez-Martínez, Juan;Acosta-Jimenez, Antonio Jose:
Projection of dual-rail DPA countermeasures in future FinFET and emerging TFET technologies. ACM Journal on Emerging Technologies in Computing Systems. 2020. Vol: 16. Núm: 3. Pág. 1-16. 10.1145/3381857.
Projection of dual-rail DPA countermeasures in future FinFET and emerging TFET technologies. ACM Journal on Emerging Technologies in Computing Systems. 2020. Vol: 16. Núm: 3. Pág. 1-16. 10.1145/3381857.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Approaching the Design of Energy Recovery Logic Circuits using Tunnel Transistors. IEEE Transactions on Nanotechnology. 2020. Vol: 19. Pág. 500-507. 10.1109/TNANO.2020.3004941.
Approaching the Design of Energy Recovery Logic Circuits using Tunnel Transistors. IEEE Transactions on Nanotechnology. 2020. Vol: 19. Pág. 500-507. 10.1109/TNANO.2020.3004941.
Avedillo-De, Maria Jose;Jiménez, Manuel;Nuñez-Martínez, Juan:
Phase Transition FETs for Improved Dynamic Logic Gates. IEEE Electron Device Letters. 2018. Vol: 39. Núm: 11. Pág. 1776-1779. 10.1109/LED.2018.2871855.
Phase Transition FETs for Improved Dynamic Logic Gates. IEEE Electron Device Letters. 2018. Vol: 39. Núm: 11. Pág. 1776-1779. 10.1109/LED.2018.2871855.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Power and Speed Evaluation of Hyper-FET Circuits. IEEE Access. 2018. Vol: 7. Pág. 6724-6732. 10.1109/ACCESS.2018.2889016.
Power and Speed Evaluation of Hyper-FET Circuits. IEEE Access. 2018. Vol: 7. Pág. 6724-6732. 10.1109/ACCESS.2018.2889016.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications. IEEE Journal of the Electron Devices Society. 2017. Vol: 5. Núm: 6. Pág. 530-534. 10.1109/JEDS.2017.2737598.
Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications. IEEE Journal of the Electron Devices Society. 2017. Vol: 5. Núm: 6. Pág. 530-534. 10.1109/JEDS.2017.2737598.
Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Insights Into the Operation of Hyper-FET-Based Circuits. IEEE Transactions on Electron Devices. 2017. Vol: 64. Núm: 9. Pág. 3912-3918. 10.1109/TED.2017.2726765.
Insights Into the Operation of Hyper-FET-Based Circuits. IEEE Transactions on Electron Devices. 2017. Vol: 64. Núm: 9. Pág. 3912-3918. 10.1109/TED.2017.2726765.
Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Impact of the RT¿level architecture on the power performance of tunnel transistor circuits. International Journal of Circuit Theory and Applications. 2017. Vol: 46. Núm: 3. Pág. 647-655. https://doi.org/10.1002/cta.2398.
Impact of the RT¿level architecture on the power performance of tunnel transistor circuits. International Journal of Circuit Theory and Applications. 2017. Vol: 46. Núm: 3. Pág. 647-655. https://doi.org/10.1002/cta.2398.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs. IEEE Transactions on Nanotechnology. 2016. Vol: 16. Núm: 1. Pág. 83-89. 10.1109/TNANO.2016.2629264.
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs. IEEE Transactions on Nanotechnology. 2016. Vol: 16. Núm: 1. Pág. 83-89. 10.1109/TNANO.2016.2629264.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose:
Comparative Analysis of Projected Tunnel and CMOS Transistors for Distinct Logic Applications Areas. IEEE Transactions on Electron Devices. 2016. Vol: 63. Núm: 12. Pág. 5012-5020. 10.1109/TED.2016.2616891.
Comparative Analysis of Projected Tunnel and CMOS Transistors for Distinct Logic Applications Areas. IEEE Transactions on Electron Devices. 2016. Vol: 63. Núm: 12. Pág. 5012-5020. 10.1109/TED.2016.2616891.
Nuñez-Martínez, Juan;Gines-Arteaga, Antonio Jose;Peralias-Macias, Eduardo;Rueda-Rueda, Adoracion:
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs. Analog Integrated Circuits and Signal Processing. 2016. Vol: 89. Núm: 3. Pág. 593-609. 10.1007/s10470-016-0870-6.
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs. Analog Integrated Circuits and Signal Processing. 2016. Vol: 89. Núm: 3. Pág. 593-609. 10.1007/s10470-016-0870-6.
Avedillo-De, Maria Jose;Nuñez-Martínez, Juan:
Improving speed of Tunnel FETs logic circuits. Electronics Letters. 2015. Vol: 51. Núm: 21. Pág. 1702-1704. 10.1049/el.2015.2416.
Improving speed of Tunnel FETs logic circuits. Electronics Letters. 2015. Vol: 51. Núm: 21. Pág. 1702-1704. 10.1049/el.2015.2416.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monoestable to Bistable Logic Elements. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014. Vol: 22. Núm: 10. Pág. 2238-2242. 10.1109/TVLSI.2013.2283306.
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monoestable to Bistable Logic Elements. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014. Vol: 22. Núm: 10. Pág. 2238-2242. 10.1109/TVLSI.2013.2283306.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Novel Pipeline Architectures based on Negative Differential Resistance Devices. Microelectronics Journal. 2013. Vol: 44. Núm: 9. Pág. 807-813. 10.1016/j.mejo.2013.06.012.
Novel Pipeline Architectures based on Negative Differential Resistance Devices. Microelectronics Journal. 2013. Vol: 44. Núm: 9. Pág. 807-813. 10.1016/j.mejo.2013.06.012.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Domino inspired MOBILE networks. Electronics Letters. 2012. Vol: 48. Núm: 5. Pág. 292-293.
Domino inspired MOBILE networks. Electronics Letters. 2012. Vol: 48. Núm: 5. Pág. 292-293.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Two-Phase RTD-CMOS Pipelined Circuits. IEEE Transactions on Nanotechnology. 2012. Vol: 11. Núm: 6. Pág. 1063-1069. 10.1109/TNANO.2012.2213839 .
Two-Phase RTD-CMOS Pipelined Circuits. IEEE Transactions on Nanotechnology. 2012. Vol: 11. Núm: 6. Pág. 1063-1069. 10.1109/TNANO.2012.2213839 .
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
RTD-CMOS Pipelined Networks for Reduced Power Consumption. IEEE Transactions on Nanotechnology. 2011. Vol: 10. Núm: 6. Pág. 1217-1220.
RTD-CMOS Pipelined Networks for Reduced Power Consumption. IEEE Transactions on Nanotechnology. 2011. Vol: 10. Núm: 6. Pág. 1217-1220.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
Simplified single-phase clock scheme for MOBILE networks. Electronics Letters. 2011. Vol: 47. Núm: 11. Pág. 648-650.
Simplified single-phase clock scheme for MOBILE networks. Electronics Letters. 2011. Vol: 47. Núm: 11. Pág. 648-650.
Nuñez-Martínez, Juan;Avedillo-De, Maria Jose;Quintana-Toledo, Jose Maria:
EFFICIENT REALISATION OF MOS-NDR THRESHOLD LOGIC GATES. Electronics Letters. 2009. Vol: 45. Núm: 23. Pág. 1158-1160.
EFFICIENT REALISATION OF MOS-NDR THRESHOLD LOGIC GATES. Electronics Letters. 2009. Vol: 45. Núm: 23. Pág. 1158-1160.
Quintana-Toledo, Jose Maria;Avedillo-De, Maria Jose;Pettenghi-Roldan, Hector;Nuñez-Martínez, Juan:
OPERATION LIMITS FOR RTD-BASED MOBILE CIRCUITS. IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2009. Vol: 56. Núm: 2. Pág. 350-363.
OPERATION LIMITS FOR RTD-BASED MOBILE CIRCUITS. IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2009. Vol: 56. Núm: 2. Pág. 350-363.
